Simulation Results: aes/unmasked

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.72 %
  • code
  • 91.61 %
  • assert
  • 97.75 %
  • func
  • 64.81 %
  • block
  • 91.71 %
  • line
  • 93.95 %
  • branch
  • 85.15 %
  • toggle
  • 97.99 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 65.519us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 56.942us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 99.402us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 54.848us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 189.233us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 232.425us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 65.567us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 54.848us 1 1 100.00
aes_csr_aliasing 2.000s 232.425us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 56.942us 1 1 100.00
aes_config_error 2.000s 57.103us 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 56.942us 1 1 100.00
aes_config_error 2.000s 57.103us 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 124.648us 1 1 100.00
aes_b2b 2.000s 66.348us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 56.942us 1 1 100.00
aes_config_error 2.000s 57.103us 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
aes_alert_reset 3.000s 75.874us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 76.224us 1 1 100.00
aes_config_error 2.000s 57.103us 1 1 100.00
aes_alert_reset 3.000s 75.874us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 160.914us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 1478.932us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 110.008us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 75.874us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 124.648us 1 1 100.00
aes_sideload 3.000s 65.643us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 312.542us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 3.000s 111.162us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 55.289us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 67.982us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 111.660us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 111.660us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 99.402us 1 1 100.00
aes_csr_rw 1.000s 54.848us 1 1 100.00
aes_csr_aliasing 2.000s 232.425us 1 1 100.00
aes_same_csr_outstanding 2.000s 66.934us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 99.402us 1 1 100.00
aes_csr_rw 1.000s 54.848us 1 1 100.00
aes_csr_aliasing 2.000s 232.425us 1 1 100.00
aes_same_csr_outstanding 2.000s 66.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 353.679us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 381.182us 1 1 100.00
aes_control_fi 2.000s 53.952us 1 1 100.00
aes_cipher_fi 7.000s 10028.475us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 211.231us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 211.231us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 211.231us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 211.231us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 330.126us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 2.000s 246.640us 1 1 100.00
aes_sec_cm 5.000s 2574.012us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 246.640us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 75.874us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 211.231us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 211.231us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 56.942us 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
aes_alert_reset 3.000s 75.874us 1 1 100.00
aes_core_fi 2.000s 93.224us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 55.289us 1 1 100.00
aes_config_error 2.000s 57.103us 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
aes_core_fi 2.000s 93.224us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 211.231us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 54.701us 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 124.648us 1 1 100.00
aes_sideload 3.000s 65.643us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 54.701us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 54.701us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 54.701us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 54.701us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 54.701us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 124.648us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 381.182us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 381.182us 1 1 100.00
aes_control_fi 2.000s 53.952us 1 1 100.00
aes_cipher_fi 7.000s 10028.475us 0 1 0.00
aes_ctr_fi 2.000s 49.947us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 381.182us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 381.182us 1 1 100.00
aes_control_fi 2.000s 53.952us 1 1 100.00
aes_cipher_fi 7.000s 10028.475us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 7.000s 10028.475us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 381.182us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 2.000s 381.182us 1 1 100.00
aes_control_fi 2.000s 53.952us 1 1 100.00
aes_ctr_fi 2.000s 49.947us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 2.000s 381.182us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 381.182us 1 1 100.00
aes_control_fi 2.000s 53.952us 1 1 100.00
aes_cipher_fi 7.000s 10028.475us 0 1 0.00
aes_ctr_fi 2.000s 49.947us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 75.874us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 381.182us 1 1 100.00
aes_control_fi 2.000s 53.952us 1 1 100.00
aes_cipher_fi 7.000s 10028.475us 0 1 0.00
aes_ctr_fi 2.000s 49.947us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 381.182us 1 1 100.00
aes_control_fi 2.000s 53.952us 1 1 100.00
aes_cipher_fi 7.000s 10028.475us 0 1 0.00
aes_ctr_fi 2.000s 49.947us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 2.000s 381.182us 1 1 100.00
aes_control_fi 2.000s 53.952us 1 1 100.00
aes_ctr_fi 2.000s 49.947us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 2.000s 381.182us 1 1 100.00
aes_ghash_fi 1.000s 57.346us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 381.182us 1 1 100.00
aes_control_fi 2.000s 53.952us 1 1 100.00
aes_cipher_fi 7.000s 10028.475us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 440.826us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 38873633221018447276350758196526635535773205842176417777760671948923459476608 147
UVM_FATAL @ 10028474901 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10028474901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 108320927687488985853883516053385657315731984732763007890157208116401517447952 1466
UVM_ERROR @ 440826193 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 440826193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---