Simulation Results: alert_handler

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.33 %
  • code
  • 91.97 %
  • assert
  • 98.33 %
  • func
  • 77.68 %
  • line
  • 99.68 %
  • branch
  • 98.29 %
  • cond
  • 92.57 %
  • toggle
  • 93.49 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 22.570s 9272.452us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.990s 147.918us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.270s 98.073us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 260.430s 23767.459us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 97.730s 1107.804us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.100s 117.661us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.270s 98.073us 1 1 100.00
alert_handler_csr_aliasing 97.730s 1107.804us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 123.370s 15122.265us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 4.430s 87.337us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 399.740s 80320.214us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 36.240s 1386.339us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 22.570s 9272.452us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 11.170s 315.301us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 25.570s 797.379us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 151.810s 6073.586us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 873.250s 63729.056us 1 1 100.00
alert_handler_lpg_stub_clk 1139.350s 115009.115us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 21.190s 1115.437us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 19.360s 2578.039us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.480s 31.005us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.460s 18.223us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 9.720s 805.455us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 9.720s 805.455us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.990s 147.918us 1 1 100.00
alert_handler_csr_rw 3.270s 98.073us 1 1 100.00
alert_handler_csr_aliasing 97.730s 1107.804us 1 1 100.00
alert_handler_same_csr_outstanding 15.960s 354.624us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.990s 147.918us 1 1 100.00
alert_handler_csr_rw 3.270s 98.073us 1 1 100.00
alert_handler_csr_aliasing 97.730s 1107.804us 1 1 100.00
alert_handler_same_csr_outstanding 15.960s 354.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 137.870s 7074.691us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 137.870s 7074.691us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 137.870s 7074.691us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 137.870s 7074.691us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 297.280s 7133.646us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
alert_handler_tl_intg_err 4.400s 102.050us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 4.400s 102.050us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 137.870s 7074.691us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 22.570s 9272.452us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 22.570s 9272.452us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 22.570s 9272.452us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 22.570s 9272.452us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 36.240s 1386.339us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 873.250s 63729.056us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 36.240s 1386.339us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 399.740s 80320.214us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 399.740s 80320.214us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.550s 1128.851us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 112.270s 10740.370us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 54504003652768108810194131614741415767357720337301009076389121830026209181798 123
UVM_ERROR @ 6073586352 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 6073586352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---