Simulation Results: chip

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.48 %
  • code
  • 84.35 %
  • assert
  • 97.37 %
  • func
  • 47.72 %
  • line
  • 93.89 %
  • branch
  • 92.26 %
  • cond
  • 87.30 %
  • toggle
  • 91.15 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
82.01%
V2S
100.00%
V3
65.38%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 125.310s 3287.235us 1 1 100.00
chip_sw_example_rom 60.290s 2696.833us 1 1 100.00
chip_sw_example_manufacturer 177.810s 2839.380us 1 1 100.00
chip_sw_example_concurrency 157.960s 2994.777us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 172.210s 4928.075us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 483.610s 5566.960us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 154.610s 4634.517us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4602.440s 36941.576us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 43.400s 2442.966us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4602.440s 36941.576us 1 1 100.00
chip_csr_rw 483.610s 5566.960us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.380s 44.459us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 332.200s 4204.216us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 332.200s 4204.216us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 332.200s 4204.216us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 360.550s 4454.209us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 360.550s 4454.209us 1 1 100.00
chip_sw_uart_tx_rx_idx1 364.910s 4258.462us 1 1 100.00
chip_sw_uart_tx_rx_idx2 351.020s 4314.217us 1 1 100.00
chip_sw_uart_tx_rx_idx3 379.430s 4978.637us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 341.550s 4355.228us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1074.540s 9221.707us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1107.240s 13512.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 197.630s 4857.798us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 197.630s 4857.798us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 171.170s 2706.240us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 127.050s 2943.836us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 152.880s 3520.930us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 600.180s 9439.426us 1 1 100.00
chip_tap_straps_testunlock0 327.690s 5496.911us 1 1 100.00
chip_tap_straps_rma 79.440s 2483.261us 1 1 100.00
chip_tap_straps_prod 78.900s 2708.106us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 196.780s 3369.417us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 783.120s 9215.566us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 475.170s 6664.756us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 475.170s 6664.756us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 608.500s 6938.839us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1584.830s 15076.251us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 340.320s 4266.386us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 555.470s 6031.403us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3411.800s 18957.487us 1 1 100.00
chip_sw_aes_enc_jitter_en 155.230s 3334.598us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 617.860s 7109.154us 1 1 100.00
chip_sw_hmac_enc_jitter_en 190.090s 2659.805us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1428.830s 12371.519us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 168.440s 2770.429us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 373.700s 4794.791us 1 1 100.00
chip_sw_clkmgr_jitter 125.560s 3175.267us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 192.630s 3734.200us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 471.730s 6562.523us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 236.940s 5312.545us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 193.070s 2707.604us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 236.940s 5312.545us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 153.090s 3277.208us 1 1 100.00
chip_sw_aes_smoketest 181.800s 2417.480us 1 1 100.00
chip_sw_aon_timer_smoketest 172.300s 3237.826us 1 1 100.00
chip_sw_clkmgr_smoketest 180.630s 3699.792us 1 1 100.00
chip_sw_csrng_smoketest 164.360s 2356.828us 1 1 100.00
chip_sw_entropy_src_smoketest 681.890s 6225.780us 1 1 100.00
chip_sw_gpio_smoketest 186.290s 2604.036us 1 1 100.00
chip_sw_hmac_smoketest 174.340s 2774.070us 1 1 100.00
chip_sw_kmac_smoketest 221.590s 2986.946us 1 1 100.00
chip_sw_otbn_smoketest 1054.700s 9562.007us 1 1 100.00
chip_sw_pwrmgr_smoketest 268.850s 5214.909us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 286.740s 5892.928us 1 1 100.00
chip_sw_rv_plic_smoketest 151.420s 3067.758us 1 1 100.00
chip_sw_rv_timer_smoketest 115.380s 2541.708us 1 1 100.00
chip_sw_rstmgr_smoketest 159.500s 3239.832us 1 1 100.00
chip_sw_sram_ctrl_smoketest 144.380s 2858.669us 1 1 100.00
chip_sw_uart_smoketest 172.520s 2436.240us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 140.250s 3434.925us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 417.730s 6029.801us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7396.130s 64897.913us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2397.750s 15644.150us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 133.800s 4846.265us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 207.100s 3006.676us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 164.610s 3380.760us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7041.780s 56715.972us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7186.240s 59119.081us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 46.910s 2533.203us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 46.910s 2533.203us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4602.440s 36941.576us 1 1 100.00
chip_same_csr_outstanding 3023.620s 27343.199us 1 1 100.00
chip_csr_hw_reset 172.210s 4928.075us 1 1 100.00
chip_csr_rw 483.610s 5566.960us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4602.440s 36941.576us 1 1 100.00
chip_same_csr_outstanding 3023.620s 27343.199us 1 1 100.00
chip_csr_hw_reset 172.210s 4928.075us 1 1 100.00
chip_csr_rw 483.610s 5566.960us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 15.000s 556.007us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.920s 51.855us 1 1 100.00
xbar_smoke_large_delays 50.880s 8861.085us 1 1 100.00
xbar_smoke_slow_rsp 41.160s 4580.189us 1 1 100.00
xbar_random_zero_delays 10.910s 157.936us 1 1 100.00
xbar_random_large_delays 73.470s 12159.492us 1 1 100.00
xbar_random_slow_rsp 290.660s 32948.632us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 22.040s 291.886us 1 1 100.00
xbar_error_and_unmapped_addr 19.770s 702.804us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 23.750s 997.082us 1 1 100.00
xbar_error_and_unmapped_addr 19.770s 702.804us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 67.870s 2935.392us 1 1 100.00
xbar_access_same_device_slow_rsp 44.170s 4031.429us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 5.410s 56.087us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 97.000s 1722.304us 1 1 100.00
xbar_stress_all_with_error 245.720s 11911.602us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 146.240s 670.990us 1 1 100.00
xbar_stress_all_with_reset_error 220.860s 3942.907us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2397.750s 15644.150us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2218.380s 26679.247us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2544.240s 15669.310us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2092.700s 11700.107us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2519.620s 15801.183us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2613.080s 20102.025us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2585.590s 16821.503us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2442.380s 14993.704us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 17.250s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 16.450s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 19.860s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 18.390s 10.140us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 16.730s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 19.770s 10.320us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 16.180s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 16.830s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 17.310s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17.580s 10.300us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 15.930s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.580s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.690s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 16.340s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.860s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.880s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.640s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 16.860s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.670s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.790s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.640s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.070s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.020s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.770s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.650s 10.100us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1922.870s 11897.970us 1 1 100.00
rom_e2e_asm_init_dev 2412.480s 16084.659us 1 1 100.00
rom_e2e_asm_init_prod 2404.710s 16630.881us 1 1 100.00
rom_e2e_asm_init_prod_end 2502.340s 15378.814us 1 1 100.00
rom_e2e_asm_init_rma 2436.880s 15067.996us 1 1 100.00
rom_e2e_keymgr_init 0 3 0.00
rom_e2e_keymgr_init_rom_ext_meas 2425.700s 18099.036us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 2455.670s 16343.273us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2413.060s 17590.534us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2550.170s 15617.955us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2943.070s 34705.760us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2943.070s 34705.760us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 182.990s 3182.610us 1 1 100.00
chip_sw_aes_enc_jitter_en 155.230s 3334.598us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 147.690s 2451.517us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 175.180s 2862.654us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1321.170s 9373.127us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 190.810s 3517.111us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 325.800s 5678.473us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 319.670s 5095.043us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 490.440s 5967.954us 1 1 100.00
chip_plic_all_irqs_10 284.760s 3512.008us 1 1 100.00
chip_plic_all_irqs_20 327.370s 4125.847us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 182.220s 3579.079us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1035.970s 14861.805us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 288.510s 4828.443us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 171.630s 3105.350us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1206.750s 8896.743us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1136.290s 9156.122us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 780.020s 8221.440us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8093.260s 255431.868us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 290.040s 4125.542us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 268.850s 5214.909us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 290.040s 4125.542us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 635.070s 8912.262us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 635.070s 8912.262us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 245.030s 7046.283us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 430.290s 5365.490us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 568.770s 5787.036us 1 1 100.00
chip_sw_aes_idle 175.180s 2862.654us 1 1 100.00
chip_sw_hmac_enc_idle 188.080s 3079.746us 1 1 100.00
chip_sw_kmac_idle 149.260s 2790.663us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 245.110s 4483.436us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 310.970s 4551.219us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 239.760s 5133.679us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 311.110s 5028.732us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 835.180s 9042.969us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 409.540s 4330.822us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 357.660s 4924.666us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 400.750s 4272.545us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 361.180s 4711.929us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 413.630s 4295.898us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 358.050s 5240.665us 1 1 100.00
chip_sw_ast_clk_outputs 608.500s 6938.839us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 730.510s 11192.301us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 400.750s 4272.545us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 361.180s 4711.929us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 340.320s 4266.386us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 555.470s 6031.403us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3411.800s 18957.487us 1 1 100.00
chip_sw_aes_enc_jitter_en 155.230s 3334.598us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 617.860s 7109.154us 1 1 100.00
chip_sw_hmac_enc_jitter_en 190.090s 2659.805us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1428.830s 12371.519us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 168.440s 2770.429us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 373.700s 4794.791us 1 1 100.00
chip_sw_clkmgr_jitter 125.560s 3175.267us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 142.700s 2744.554us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 408.030s 5220.160us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 676.700s 7864.969us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3106.820s 25243.780us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 186.700s 3112.732us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 156.790s 2972.341us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 930.340s 10306.834us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 160.670s 3624.068us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 354.940s 5848.469us 1 1 100.00
chip_sw_flash_init_reduced_freq 1333.770s 26622.035us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3213.040s 33177.834us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 608.500s 6938.839us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 381.260s 4650.196us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 269.680s 3884.892us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 319.670s 5095.043us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1206.750s 8896.743us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 784.960s 6090.515us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 202.140s 3651.440us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 404.760s 5532.031us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 147.270s 2350.392us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 1964.250s 12537.290us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 162.070s 2810.517us 1 1 100.00
chip_sw_edn_entropy_reqs 893.590s 7401.676us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 162.070s 2810.517us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 784.960s 6090.515us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 139.920s 2853.483us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1504.030s 25493.033us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 593.900s 5339.283us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 555.470s 6031.403us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 350.020s 3691.901us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 340.320s 4266.386us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3441.760s 44445.998us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1504.030s 25493.033us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 196.420s 3387.444us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 755.400s 7831.892us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 144.060s 2922.961us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3441.760s 44445.998us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 144.060s 2922.961us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 144.060s 2922.961us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 144.060s 2922.961us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 144.060s 2922.961us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 319.670s 5095.043us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 226.910s 10761.722us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 539.390s 5180.495us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 378.560s 5190.941us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 378.560s 5190.941us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 176.820s 3312.026us 1 1 100.00
chip_sw_hmac_enc_jitter_en 190.090s 2659.805us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 188.080s 3079.746us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 957.840s 8072.859us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 693.900s 6348.090us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 345.550s 4756.874us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 381.380s 4848.130us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 467.350s 5878.160us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 236.190s 3738.648us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 755.400s 7831.892us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1428.830s 12371.519us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1512.200s 12967.406us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1321.170s 9373.127us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2029.860s 10960.607us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 181.920s 3451.893us 1 1 100.00
chip_sw_kmac_mode_kmac 186.550s 3411.899us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 168.440s 2770.429us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 755.400s 7831.892us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 303.000s 4677.794us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 115.700s 3389.665us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1133.140s 8493.513us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 149.260s 2790.663us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 325.800s 5678.473us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 600.180s 9439.426us 1 1 100.00
chip_tap_straps_rma 79.440s 2483.261us 1 1 100.00
chip_tap_straps_prod 78.900s 2708.106us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 156.910s 2523.611us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 303.000s 4677.794us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 303.000s 4677.794us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 303.000s 4677.794us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1777.350s 12122.767us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_prim_tl_access 226.910s 10761.722us 1 1 100.00
chip_rv_dm_lc_disabled 83.030s 4000.853us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 144.060s 2922.961us 0 1 0.00
chip_sw_flash_rma_unlocked 3441.760s 44445.998us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 220.580s 3782.648us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 587.360s 6638.572us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 436.410s 6355.457us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 574.940s 7706.945us 0 1 0.00
chip_sw_lc_ctrl_transition 303.000s 4677.794us 1 1 100.00
chip_sw_keymgr_key_derivation 755.400s 7831.892us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 335.000s 8894.026us 1 1 100.00
chip_sw_sram_ctrl_execution_main 470.130s 6808.524us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 730.510s 11192.301us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 409.540s 4330.822us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 357.660s 4924.666us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 400.750s 4272.545us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 361.180s 4711.929us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 413.630s 4295.898us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 358.050s 5240.665us 1 1 100.00
chip_tap_straps_dev 600.180s 9439.426us 1 1 100.00
chip_tap_straps_rma 79.440s 2483.261us 1 1 100.00
chip_tap_straps_prod 78.900s 2708.106us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 191.760s 3354.579us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 101.690s 2930.161us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 98.060s 3124.837us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 139.060s 2834.236us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 83.030s 4000.853us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2073.440s 37044.657us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 686.980s 10835.030us 0 1 0.00
chip_sw_lc_walkthrough_prod 601.100s 7709.737us 0 1 0.00
chip_sw_lc_walkthrough_prodend 582.260s 11280.661us 1 1 100.00
chip_sw_lc_walkthrough_rma 366.110s 5979.188us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2073.440s 37044.657us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 74.710s 2788.477us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 54.850s 1941.336us 1 1 100.00
rom_volatile_raw_unlock 80.770s 3077.361us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3520.460s 17068.603us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3411.800s 18957.487us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 568.770s 5787.036us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 568.770s 5787.036us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 568.770s 5787.036us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 308.910s 3364.385us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 303.000s 4677.794us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1504.030s 25493.033us 1 1 100.00
chip_sw_otbn_mem_scramble 308.910s 3364.385us 1 1 100.00
chip_sw_keymgr_key_derivation 755.400s 7831.892us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 296.400s 4784.687us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 155.890s 2751.403us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1504.030s 25493.033us 1 1 100.00
chip_sw_otbn_mem_scramble 308.910s 3364.385us 1 1 100.00
chip_sw_keymgr_key_derivation 755.400s 7831.892us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 296.400s 4784.687us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 155.890s 2751.403us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 303.000s 4677.794us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 305.030s 5538.302us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 156.910s 2523.611us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 226.910s 10761.722us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 220.580s 3782.648us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 587.360s 6638.572us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 436.410s 6355.457us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 574.940s 7706.945us 0 1 0.00
chip_sw_lc_ctrl_transition 303.000s 4677.794us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 226.910s 10761.722us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 796.290s 7367.138us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 270.540s 7354.906us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1293.120s 24641.349us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 256.490s 7401.650us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 276.060s 6794.646us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 471.660s 6029.381us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 811.880s 20745.150us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 793.090s 13097.508us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 635.070s 8912.262us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 712.490s 12326.832us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 335.280s 3794.012us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 270.540s 7354.906us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 229.570s 5005.460us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2298.810s 40120.340us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 356.070s 8131.828us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 291.070s 6199.664us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 207.530s 5184.563us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 838.400s 9974.517us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 960.340s 10445.061us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1958.520s 33835.417us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 166.150s 3060.432us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 319.670s 5095.043us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 335.000s 8894.026us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 335.000s 8894.026us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 960.340s 10445.061us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 207.530s 5184.563us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 335.280s 3794.012us 1 1 100.00
chip_sw_pwrmgr_smoketest 268.850s 5214.909us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 269.060s 5277.939us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 281.310s 4271.262us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 310.720s 4975.710us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1035.970s 14861.805us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 132.360s 2541.316us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 319.670s 5095.043us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1136.290s 9156.122us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 488.850s 5121.772us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 503.150s 4347.390us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 183.540s 3109.530us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 155.890s 2751.403us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 281.310s 4271.262us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 281.310s 4271.262us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 689.710s 10347.238us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 875.920s 13750.621us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 269.060s 5277.939us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 161.740s 2458.012us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 372.920s 6762.658us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 79.440s 2483.261us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 83.030s 4000.853us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 490.440s 5967.954us 1 1 100.00
chip_plic_all_irqs_10 284.760s 3512.008us 1 1 100.00
chip_plic_all_irqs_20 327.370s 4125.847us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 146.330s 2578.909us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 187.840s 3186.066us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2397.750s 15644.150us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 404.360s 5611.838us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 252.290s 3898.178us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 186.340s 3040.360us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 164.280s 3093.121us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 296.400s 4784.687us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 373.700s 4794.791us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 542.180s 8219.215us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 469.940s 8398.953us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 470.130s 6808.524us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 319.670s 5095.043us 1 1 100.00
chip_sw_data_integrity_escalation 475.170s 6664.756us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 838.400s 9974.517us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1278.230s 24032.499us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 162.700s 2768.829us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 226.130s 4086.004us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 340.750s 4703.885us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1278.230s 24032.499us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1278.230s 24032.499us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2322.130s 21061.007us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2322.130s 21061.007us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 255.230s 5170.243us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2943.070s 34705.760us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 143.270s 3047.210us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 145.090s 2804.366us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 302.030s 4260.606us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 354.110s 4571.752us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1098.120s 8330.467us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5154.000s 31336.771us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1892.340s 12359.672us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 142.350s 2959.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 174.200s 2614.822us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 159.740s 3090.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9028.640s 71907.089us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1068.650s 6708.948us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 161.610s 2990.245us 0 1 0.00
rom_e2e_jtag_debug_dev 157.600s 4393.053us 0 1 0.00
rom_e2e_jtag_debug_rma 400.340s 5727.727us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 66.920s 2594.742us 0 1 0.00
rom_e2e_jtag_inject_dev 53.280s 2393.334us 0 1 0.00
rom_e2e_jtag_inject_rma 85.740s 3336.793us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 8.521s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 289.970s 3638.261us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 332.410s 3059.627us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 851.110s 5909.379us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1354.120s 11043.808us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 224.410s 2591.504us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 556.320s 5326.542us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 168.700s 2856.199us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 212.930s 3668.504us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 253.350s 6019.766us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 373.240s 5658.631us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 960.340s 10445.061us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 161.610s 2990.245us 0 1 0.00
rom_e2e_jtag_debug_dev 157.600s 4393.053us 0 1 0.00
rom_e2e_jtag_debug_rma 400.340s 5727.727us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 415.420s 5893.832us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 319.670s 5095.043us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5440.680s 38794.895us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5440.680s 38794.895us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 161.070s 3419.938us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 360.550s 4454.209us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2935.690s 19235.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 163.900s 2963.421us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 399.440s 5382.717us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.900s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 164.390s 3459.846us 1 1 100.00
chip_sw_otp_ctrl_descrambling 161.530s 2437.222us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 301.050s 4317.796us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.147s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 187.460s 3049.984us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 67331651858336711380713954695611765123687561176727644266444302309127058835226 217
UVM_ERROR @ 2533.203300 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@33099) { a_addr: 'h10794 a_data: 'h4d4a169b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h18103 d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2533.203300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 53180431080181623372008500461095558723957091609096085998034107533397558145417 224
UVM_ERROR @ 2442.965928 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31843) { a_addr: 'h106d0 a_data: 'ha1c06907 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h1a202 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2442.965928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 35202763603774955219617627610947878351696052676174506047631775332610237565203 333
UVM_ERROR @ 4271.261764 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@114375) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 4271.261764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 68370806784043967979529410222523096589657851719156642003075341800279920697607 225
UVM_ERROR @ 4000.853023 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105f8 read out mismatch
UVM_INFO @ 4000.853023 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 65235789860856013352304783379508386223935929904266931950953012360057161550223 451
UVM_ERROR @ 2706.240000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 2706.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 51461971726653022622657392660078938803539143017007996796854428533743544488563 320
UVM_ERROR @ 3898.177864 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3898.177864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 54535151890427254011137841714474141396796829517367259715609498689626285253021 309
UVM_ERROR @ 2922.960574 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 2922.960574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 101261113875035012792958421191953482857878272317515047396035338444864660498336 342
UVM_ERROR @ 7706.944989 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7706.944989 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 73904091069396568661219499253379135296952944819370057459094832442582736499989 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3668.504016 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3668.504016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 95583854279799977939124300307512956495265236297521351699295843377796688805597 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3651.439928 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3651.439928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 68148350975134272701574685781003786991423251043576995911680995956852369109410 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 19938884026558364401968963637533292583518844242266402971509900970040994429184 369
UVM_ERROR @ 10835.029992 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 10835.029992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 60296492510152242138927612673803598528652221305140684343917756971497962546974 369
UVM_ERROR @ 7709.737010 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 7709.737010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 45073361573474528660824443956579425423544954546769544668397914709398167386482 341
UVM_ERROR @ 5979.188216 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 5979.188216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 57665716701432127910393938267615398456858270900625613051579211970224117300539 315
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 5184.563000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5184.563000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 111980555647834190326482609586076323374243652730643036006293206518100615922624 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6794.646000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6794.646000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 113537203424494508613051606045502332478463523911118666844305155857228662243206 332
UVM_ERROR @ 34705.759956 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34705.759956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 59862900466857947481159774844056444935408618314995047350784268880127957480424 307
UVM_ERROR @ 3517.111478 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
UVM_INFO @ 3517.111478 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 69424524101454718875975697224118782202900595392812074866666154268301936046594 308
UVM_ERROR @ 3105.350288 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3105.350288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 19578276436111036067147653561833388884847826543245336430287536436534146148967 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 67525092314322175290513450012256541275767136708131936993918704288986109726985 343
UVM_ERROR @ 3638.261275 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3638.261275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 81420366087223634066831210388583123984684777321050518837716912325402873776468 None
---- STDERR ----
Another command (pid=1930693) is running. Waiting for it to complete on the server (server_pid=934140)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 87914927839810401782831067414081550192759161841582720435787067019612490547838 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 29424884391297354228632027493990877536156025311587960581659285128506865665911 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 114637880924102549967498199888202969162304742605688986257663933740953233499111 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 68683472013173604213563395418605446827277596076745757855996821753334393803477 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 34731628161712831364166469951078876537619412487360973904462286195493430691485 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 48562600405702552726436721702619702566915411956764316944848897616634285138820 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 81309639124838305637832021689940121475820165223662075565875381600690376109882 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 24330540755510175541202603930003583046195912242182181857038710276699881209713 312
UVM_ERROR @ 3006.676000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3006.676000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 67760308569907666620442316630783160196363840885724520625124195061444607988104 318
UVM_ERROR @ 3380.760000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3380.760000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 67041463425509109145204115050598795823706916820992351670001332460073950533824 327
UVM_ERROR @ 15076.250754 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 15076.250754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 17982297150589342668161348936029711096389185031162309371788158972940077173701 351
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 23705134252972630659193161685678554121867154982715803820548176486511955214642 348
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 74538317251507805544857600843735990755054644978221062207664646639960706443578 351
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 91402255125873325661682821668863998017579435605976104864846369116296841080039 349
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 10291026706439125375284263027698124414676642935944404208875294153099299439380 350
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 5326010938172968029596664764414871972042367337227154556478872273082865806549 347
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 33118629647192361248248190506175665427455831664895517053327431610265552769861 346
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 4110835332558293483085098074715938536318480713043373917109505256778399475257 347
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 89540989751308470755039404156873475229378869346105067955462235763728601377262 349
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 36387685177450292172135559471538379548097992928295486370957733918628538001508 349
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 75821866427949524793497900071685901061096486264564490546021490717848589638291 359
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 109296947463613712886501505388432428706718087297528934900623734039201802916188 360
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 64708217568809992968793246077972924260939037372655745349896297111185632587626 359
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 105793350814589849691428128956523157235379322075217795610804268345977408152912 325
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 80685655163200089668528641592168268399720926849005870010608103582768818769826 323
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 42057435833996420407146563553699014280481010894880201248209802841243573683545 324
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 64689672683055006359580746059696155231097885487991072150943129596614477949914 359
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 62626508253853737033559006777859058307776245864526661210088426572951167464094 325
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 41119576573180282230715078441461214504771958464366299908405570278031923701771 360
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 59437371986414376369447451494869525346233779387952709279398506330175201769085 325
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 12461423609012834370795757691348399165140371024707536449103871608470857182172 323
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 28005196701305814228109634031388240190769014992354434050125897307586966166136 324
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 7589193826846513301411437511089839938119669593774536577257236942486574239790 325
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 66579272131246049202772103993287823855061154073998084657547623504085888727038 323
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 93491694824985348939386723398331381286380317318172001803146706291285164270383 322
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_test_unlocked0 56437108979308127213573757177168856830110905698525035876177414027159213571680 318
UVM_ERROR @ 2990.245125 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
UVM_INFO @ 2990.245125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 72226772811918095945929548070774024007261731899847608299071479004248481341078 319
UVM_ERROR @ 18099.035672 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 18099.035672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 90938726713307884595339472529324148541065535130159765599753883861798305305163 319
UVM_ERROR @ 16343.272917 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16343.272917 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 26672937548880444855864728583890844052531113725603640579177215662228579554733 319
UVM_ERROR @ 17590.533972 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 17590.533972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 113166582964103013014992726155970979249382000890379175625847498054761189433382 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 6029.800538 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6029.800538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---