Simulation Results: clkmgr

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.45 %
  • code
  • 98.03 %
  • assert
  • 94.92 %
  • func
  • 84.39 %
  • line
  • 98.94 %
  • branch
  • 98.62 %
  • cond
  • 93.40 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.850s 38.835us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.780s 17.990us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.160s 209.470us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.170s 263.506us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.030s 70.152us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.900s 30.037us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.160s 209.470us 1 1 100.00
clkmgr_csr_aliasing 1.030s 70.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.720s 43.078us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.920s 26.432us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.800s 119.189us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.680s 29.935us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.850s 38.835us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 3.200s 1090.340us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.750s 1340.589us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 3.200s 1090.340us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 12.820s 2959.686us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.660s 16.709us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.900s 309.038us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.900s 309.038us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 17.990us 1 1 100.00
clkmgr_csr_rw 1.160s 209.470us 1 1 100.00
clkmgr_csr_aliasing 1.030s 70.152us 1 1 100.00
clkmgr_same_csr_outstanding 1.500s 184.783us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 17.990us 1 1 100.00
clkmgr_csr_rw 1.160s 209.470us 1 1 100.00
clkmgr_csr_aliasing 1.030s 70.152us 1 1 100.00
clkmgr_same_csr_outstanding 1.500s 184.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_tl_intg_err 1.360s 71.531us 1 1 100.00
clkmgr_sec_cm 1.480s 184.414us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 91.352us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 91.352us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 91.352us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 91.352us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.410s 113.375us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.360s 71.531us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 3.200s 1090.340us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.750s 1340.589us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 91.352us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.800s 32.253us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.790s 55.657us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.710s 27.921us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.690s 18.825us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.820s 28.002us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.160s 209.470us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.480s 184.414us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.160s 209.470us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.160s 209.470us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.480s 184.414us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.300s 1314.151us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 16.820s 4091.823us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger!
clkmgr_shadow_reg_errors_with_csr_rw 45349442072942916990451522491443554019574422312440875054422441122516047328072 75
UVM_ERROR @ 113375255 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 113375255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 10769870489187441052213849115622789062003504702548641682444660990525342554713 204
UVM_ERROR @ 184413657 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 184413657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---