Simulation Results: csrng

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.93 %
  • code
  • 92.35 %
  • assert
  • 93.23 %
  • func
  • 75.20 %
  • block
  • 97.05 %
  • line
  • 97.80 %
  • branch
  • 92.59 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 51.354us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 16.352us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 30.339us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 9.000s 367.429us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 153.774us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 104.190us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 30.339us 1 1 100.00
csrng_csr_aliasing 4.000s 153.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 498.689us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 7.000s 398.893us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 7.000s 398.893us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 521.000s 54837.819us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 27.020us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 105.319us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 52.598us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 52.598us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.352us 1 1 100.00
csrng_csr_rw 1.000s 30.339us 1 1 100.00
csrng_csr_aliasing 4.000s 153.774us 1 1 100.00
csrng_same_csr_outstanding 3.000s 52.351us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.352us 1 1 100.00
csrng_csr_rw 1.000s 30.339us 1 1 100.00
csrng_csr_aliasing 4.000s 153.774us 1 1 100.00
csrng_same_csr_outstanding 3.000s 52.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 90.691us 1 1 100.00
csrng_tl_intg_err 5.000s 142.561us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 14.065us 1 1 100.00
csrng_csr_rw 1.000s 30.339us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 498.689us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 521.000s 54837.819us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
csrng_sec_cm 4.000s 90.691us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
csrng_sec_cm 4.000s 90.691us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
csrng_sec_cm 4.000s 90.691us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
csrng_sec_cm 4.000s 90.691us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
csrng_sec_cm 4.000s 90.691us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 498.689us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 521.000s 54837.819us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 498.689us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 142.561us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
csrng_sec_cm 4.000s 90.691us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
csrng_sec_cm 4.000s 90.691us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 81.164us 1 1 100.00
csrng_err 1.000s 25.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits
csrng_cmds 71259722013482325471727198301043359770681558876080653846046767549287677650888 133
UVM_ERROR @ 398892785 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (12847684 [0xc40a44] vs 0 [0x0]) reg name: csrng_reg_block.genbits
UVM_INFO @ 398892785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
csrng_stress_all_with_rand_reset 1205197513569863764792889280628701419675146890900682136357538832175543641548 None
Job timed out after 180 minutes