Simulation Results: edn/edn0

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.91 %
  • code
  • 79.55 %
  • assert
  • 95.01 %
  • func
  • 80.16 %
  • line
  • 97.17 %
  • branch
  • 90.10 %
  • cond
  • 85.37 %
  • toggle
  • 76.17 %
  • FSM
  • 48.92 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.990s 27.252us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.990s 25.347us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 11.483us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.620s 66.396us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.210s 34.302us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.990s 86.544us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 11.483us 1 1 100.00
edn_csr_aliasing 1.210s 34.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.800s 249.996us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.800s 249.996us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.800s 249.996us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.960s 26.524us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.850s 55.023us 1 1 100.00
errs 1 1 100.00
edn_err 1.060s 36.643us 1 1 100.00
disable 2 2 100.00
edn_disable 0.840s 50.041us 1 1 100.00
edn_disable_auto_req_mode 1.020s 36.476us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.660s 286.316us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 63.144us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.980s 69.491us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.890s 462.624us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.890s 462.624us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.990s 25.347us 1 1 100.00
edn_csr_rw 0.770s 11.483us 1 1 100.00
edn_csr_aliasing 1.210s 34.302us 1 1 100.00
edn_same_csr_outstanding 0.870s 24.051us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.990s 25.347us 1 1 100.00
edn_csr_rw 0.770s 11.483us 1 1 100.00
edn_csr_aliasing 1.210s 34.302us 1 1 100.00
edn_same_csr_outstanding 0.870s 24.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.060s 278.154us 1 1 100.00
edn_sec_cm 6.760s 2329.953us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 28.790us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.850s 55.023us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.760s 2329.953us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.760s 2329.953us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.760s 2329.953us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.760s 2329.953us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.850s 55.023us 1 1 100.00
edn_sec_cm 6.760s 2329.953us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.850s 55.023us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.060s 278.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 48.400s 25762.946us 1 1 100.00