Simulation Results: edn/edn1

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.46 %
  • code
  • 82.20 %
  • assert
  • 97.14 %
  • func
  • 80.04 %
  • line
  • 97.88 %
  • branch
  • 92.64 %
  • cond
  • 89.54 %
  • toggle
  • 87.74 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 46.721us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 19.517us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 41.183us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.480s 272.218us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 229.779us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.040s 154.312us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 41.183us 1 1 100.00
edn_csr_aliasing 1.150s 229.779us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.020s 61.170us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.020s 61.170us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.020s 61.170us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.900s 20.649us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 62.089us 1 1 100.00
errs 1 1 100.00
edn_err 0.860s 21.540us 1 1 100.00
disable 2 2 100.00
edn_disable 0.720s 35.817us 1 1 100.00
edn_disable_auto_req_mode 0.880s 231.525us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.310s 386.021us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.960s 53.829us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.810s 51.089us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.770s 213.040us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.770s 213.040us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 19.517us 1 1 100.00
edn_csr_rw 0.840s 41.183us 1 1 100.00
edn_csr_aliasing 1.150s 229.779us 1 1 100.00
edn_same_csr_outstanding 0.770s 34.181us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 19.517us 1 1 100.00
edn_csr_rw 0.840s 41.183us 1 1 100.00
edn_csr_aliasing 1.150s 229.779us 1 1 100.00
edn_same_csr_outstanding 0.770s 34.181us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.930s 772.808us 1 1 100.00
edn_sec_cm 3.660s 443.818us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 42.017us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 62.089us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.660s 443.818us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.660s 443.818us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.660s 443.818us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.660s 443.818us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 62.089us 1 1 100.00
edn_sec_cm 3.660s 443.818us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 62.089us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.930s 772.808us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 15.440s 4293.422us 1 1 100.00