Simulation Results: entropy_src/rng_4bits

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.52 %
  • code
  • 89.23 %
  • assert
  • 83.91 %
  • func
  • 53.40 %
  • block
  • 94.77 %
  • line
  • 97.45 %
  • branch
  • 87.12 %
  • toggle
  • 76.54 %
  • FSM
  • 95.83 %
Validation stages
V1
100.00%
V2
93.75%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 321.307us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 37.502us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 18.370us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 6.000s 381.046us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 71.059us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 115.660us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 18.370us 1 1 100.00
entropy_src_csr_aliasing 3.000s 71.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 321.307us 1 1 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
entropy_src_fw_ov 66.000s 6850.252us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 66.000s 6850.252us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 414.000s 16065.653us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
entropy_src_intr 14.000s 364.602us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
entropy_src_functional_alerts 5.000s 624.472us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 12.000s 8915.348us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 45.249us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 4.000s 1662.599us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 18.590us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 38.738us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 670.878us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 670.878us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 37.502us 1 1 100.00
entropy_src_csr_rw 2.000s 18.370us 1 1 100.00
entropy_src_csr_aliasing 3.000s 71.059us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 73.390us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 37.502us 1 1 100.00
entropy_src_csr_rw 2.000s 18.370us 1 1 100.00
entropy_src_csr_aliasing 3.000s 71.059us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 73.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 99.357us 1 1 100.00
entropy_src_tl_intg_err 2.000s 188.131us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
entropy_src_cfg_regwen 2.000s 21.471us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
entropy_src_fw_ov 66.000s 6850.252us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 45.249us 1 1 100.00
entropy_src_sec_cm 3.000s 99.357us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 45.249us 1 1 100.00
entropy_src_sec_cm 3.000s 99.357us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 38.000s 17358.917us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 45.249us 1 1 100.00
entropy_src_sec_cm 3.000s 99.357us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 45.249us 1 1 100.00
entropy_src_sec_cm 3.000s 99.357us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 45.249us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 624.472us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 188.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 103.000s 7080.705us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly
entropy_src_fw_ov 75531629031783044120929213795683755283120602362492863145789356860391700033339 962
UVM_ERROR @ 6850251551 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly
UVM_INFO @ 6850251551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---