Simulation Results: flash_ctrl

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.81 %
  • code
  • 94.45 %
  • assert
  • 96.76 %
  • func
  • 96.22 %
  • line
  • 95.99 %
  • branch
  • 97.21 %
  • cond
  • 93.86 %
  • toggle
  • 98.12 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 69.790s 32.315us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.910s 31.472us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 13.020s 52.986us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 5.710s 21.961us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 28.680s 1625.603us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 35.010s 881.465us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 10.210s 699.274us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 5.710s 21.961us 1 1 100.00
flash_ctrl_csr_aliasing 35.010s 881.465us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.370s 29.305us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.550s 35.089us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.620s 50.688us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 45.010s 70.118us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1289.210s 334817.413us 1 1 100.00
flash_ctrl_hw_rma_reset 627.620s 160174.297us 1 1 100.00
flash_ctrl_lcmgr_intg 6.400s 39.349us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1577.970s 574037.768us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 121.680s 3522.972us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 143.650s 5455.249us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 3012.850s 287593.037us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 36.940s 111.150us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.270s 124.072us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.560s 42.293us 1 1 100.00
flash_ctrl_re_evict 16.360s 228.302us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 42.900s 182.294us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 42.900s 182.294us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 398.170s 15470.110us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.320s 938.535us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 99.100s 71.611us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 316.550s 3875.823us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 291.940s 4137.459us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 809.200s 3099.722us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.630s 78.872us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 108.230s 2054.317us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 12.220s 66.900us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 9.630s 16.232us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 367.900s 276.291us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 36.920s 1804.652us 1 1 100.00
flash_ctrl_otp_reset 56.170s 40.978us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1289.210s 334817.413us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 96.570s 791.200us 1 1 100.00
flash_ctrl_intr_wr 50.520s 5329.714us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 83.440s 5894.082us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 106.110s 19866.417us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 38.890s 1486.497us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 36.050s 1337.188us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.100s 130.444us 1 1 100.00
flash_ctrl_ro_derr 84.040s 5704.179us 1 1 100.00
flash_ctrl_rw_derr 145.160s 3745.687us 1 1 100.00
flash_ctrl_derr_detect 111.140s 972.029us 1 1 100.00
flash_ctrl_integrity 335.030s 3523.004us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.610s 41.959us 1 1 100.00
flash_ctrl_ro_serr 78.580s 702.163us 1 1 100.00
flash_ctrl_rw_serr 161.380s 2205.675us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 59.610s 9309.623us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 50.950s 3899.346us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 157.050s 2964.130us 1 1 100.00
flash_ctrl_write_word_sweep 6.670s 153.646us 1 1 100.00
flash_ctrl_read_word_sweep 5.940s 119.679us 1 1 100.00
flash_ctrl_ro 64.200s 3267.887us 1 1 100.00
flash_ctrl_rw 328.180s 14078.700us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.410s 690.163us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 643.500s 91558.393us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 82.440s 10020.098us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.530s 45.399us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.480s 20.052us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.110s 73.460us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.110s 73.460us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.020s 52.986us 1 1 100.00
flash_ctrl_csr_rw 5.710s 21.961us 1 1 100.00
flash_ctrl_csr_aliasing 35.010s 881.465us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.140s 236.831us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.020s 52.986us 1 1 100.00
flash_ctrl_csr_rw 5.710s 21.961us 1 1 100.00
flash_ctrl_csr_aliasing 35.010s 881.465us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.140s 236.831us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 19.200s 90.934us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 19.200s 90.934us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 19.200s 90.934us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 19.200s 90.934us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 16.490s 227.409us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 369.660s 985.025us 1 1 100.00
flash_ctrl_sec_cm 1530.010s 1666.621us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 369.660s 985.025us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 369.660s 985.025us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 12.580s 64.838us 1 1 100.00
flash_ctrl_wr_intg 6.630s 62.192us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 69.790s 32.315us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 56.170s 40.978us 1 1 100.00
flash_ctrl_disable 12.220s 66.900us 1 1 100.00
flash_ctrl_sec_info_access 42.320s 1957.275us 1 1 100.00
flash_ctrl_connect 9.630s 16.232us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.190s 43.681us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.710s 21.961us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 19.200s 90.934us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.710s 21.961us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 19.200s 90.934us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.710s 21.961us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 19.200s 90.934us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 12.220s 66.900us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 12.580s 64.838us 1 1 100.00
flash_ctrl_access_after_disable 6.330s 38.630us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.370s 27.981us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 12.220s 66.900us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.320s 938.535us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 328.180s 14078.700us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 161.380s 2205.675us 1 1 100.00
flash_ctrl_rw_derr 145.160s 3745.687us 1 1 100.00
flash_ctrl_integrity 335.030s 3523.004us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1289.210s 334817.413us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.010s 1666.621us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.010s 1666.621us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.010s 1666.621us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1530.010s 1666.621us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 7.670s 887.422us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 8.470s 75.371us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.710s 93.313us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1530.010s 1666.621us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.010s 1666.621us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.010s 1666.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.820s 251.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 337.780s 488.728us 1 1 100.00