Simulation Results: hmac

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.21 %
  • code
  • 97.02 %
  • assert
  • 96.70 %
  • func
  • 43.91 %
  • line
  • 99.59 %
  • branch
  • 98.68 %
  • cond
  • 95.67 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.640s 786.729us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.870s 65.530us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.900s 18.849us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.220s 1629.970us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.590s 55.035us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.860s 100.831us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.900s 18.849us 1 1 100.00
hmac_csr_aliasing 2.590s 55.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 24.400s 13874.773us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 62.420s 1483.575us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.240s 161.126us 1 1 100.00
hmac_test_sha384_vectors 20.120s 232.000us 1 1 100.00
hmac_test_sha512_vectors 19.440s 866.172us 1 1 100.00
hmac_test_hmac256_vectors 12.530s 695.365us 1 1 100.00
hmac_test_hmac384_vectors 6.430s 205.636us 1 1 100.00
hmac_test_hmac512_vectors 12.130s 599.359us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 16.880s 4717.990us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 761.610s 11212.522us 1 1 100.00
error 1 1 100.00
hmac_error 65.770s 12836.312us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 72.590s 2428.203us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.640s 786.729us 1 1 100.00
hmac_long_msg 24.400s 13874.773us 1 1 100.00
hmac_back_pressure 62.420s 1483.575us 1 1 100.00
hmac_datapath_stress 761.610s 11212.522us 1 1 100.00
hmac_burst_wr 16.880s 4717.990us 1 1 100.00
hmac_stress_all 1752.610s 721078.307us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.640s 786.729us 1 1 100.00
hmac_long_msg 24.400s 13874.773us 1 1 100.00
hmac_back_pressure 62.420s 1483.575us 1 1 100.00
hmac_datapath_stress 761.610s 11212.522us 1 1 100.00
hmac_wipe_secret 72.590s 2428.203us 1 1 100.00
hmac_test_sha256_vectors 8.240s 161.126us 1 1 100.00
hmac_test_sha384_vectors 20.120s 232.000us 1 1 100.00
hmac_test_sha512_vectors 19.440s 866.172us 1 1 100.00
hmac_test_hmac256_vectors 12.530s 695.365us 1 1 100.00
hmac_test_hmac384_vectors 6.430s 205.636us 1 1 100.00
hmac_test_hmac512_vectors 12.130s 599.359us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.640s 786.729us 1 1 100.00
hmac_long_msg 24.400s 13874.773us 1 1 100.00
hmac_back_pressure 62.420s 1483.575us 1 1 100.00
hmac_datapath_stress 761.610s 11212.522us 1 1 100.00
hmac_burst_wr 16.880s 4717.990us 1 1 100.00
hmac_error 65.770s 12836.312us 1 1 100.00
hmac_wipe_secret 72.590s 2428.203us 1 1 100.00
hmac_test_sha256_vectors 8.240s 161.126us 1 1 100.00
hmac_test_sha384_vectors 20.120s 232.000us 1 1 100.00
hmac_test_sha512_vectors 19.440s 866.172us 1 1 100.00
hmac_test_hmac256_vectors 12.530s 695.365us 1 1 100.00
hmac_test_hmac384_vectors 6.430s 205.636us 1 1 100.00
hmac_test_hmac512_vectors 12.130s 599.359us 1 1 100.00
hmac_stress_all 1752.610s 721078.307us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1752.610s 721078.307us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.740s 14.818us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.730s 20.208us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.940s 122.197us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.940s 122.197us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.870s 65.530us 1 1 100.00
hmac_csr_rw 0.900s 18.849us 1 1 100.00
hmac_csr_aliasing 2.590s 55.035us 1 1 100.00
hmac_same_csr_outstanding 2.230s 161.011us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.870s 65.530us 1 1 100.00
hmac_csr_rw 0.900s 18.849us 1 1 100.00
hmac_csr_aliasing 2.590s 55.035us 1 1 100.00
hmac_same_csr_outstanding 2.230s 161.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 2.390s 328.282us 1 1 100.00
hmac_sec_cm 0.890s 213.509us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.390s 328.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.640s 786.729us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.200s 21.285us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 75.090s 3818.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.660s 47.322us 1 1 100.00