Simulation Results: keymgr

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.13 %
  • code
  • 96.76 %
  • assert
  • 97.49 %
  • func
  • 67.14 %
  • line
  • 98.96 %
  • branch
  • 97.99 %
  • cond
  • 93.84 %
  • toggle
  • 97.68 %
  • FSM
  • 95.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.080s 81.506us 1 1 100.00
random 1 1 100.00
keymgr_random 4.850s 121.036us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.050s 24.123us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.780s 39.100us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 11.040s 1693.648us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 7.550s 1907.353us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.130s 27.426us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.780s 39.100us 1 1 100.00
keymgr_csr_aliasing 7.550s 1907.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 1.890s 65.302us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 4.570s 173.446us 1 1 100.00
keymgr_sideload_kmac 6.920s 1574.973us 1 1 100.00
keymgr_sideload_aes 2.340s 344.523us 1 1 100.00
keymgr_sideload_otbn 2.020s 39.088us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.870s 210.451us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 3.620s 716.145us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.900s 609.028us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 2.120s 71.380us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.420s 236.687us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.580s 211.842us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 130.900s 8478.107us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.770s 12.579us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 1.090s 10.731us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.330s 159.243us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.330s 159.243us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.050s 24.123us 1 1 100.00
keymgr_csr_rw 0.780s 39.100us 1 1 100.00
keymgr_csr_aliasing 7.550s 1907.353us 1 1 100.00
keymgr_same_csr_outstanding 1.470s 175.580us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.050s 24.123us 1 1 100.00
keymgr_csr_rw 0.780s 39.100us 1 1 100.00
keymgr_csr_aliasing 7.550s 1907.353us 1 1 100.00
keymgr_same_csr_outstanding 1.470s 175.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
keymgr_tl_intg_err 3.580s 412.355us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.680s 216.801us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.680s 216.801us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.680s 216.801us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.680s 216.801us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.990s 377.380us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.580s 412.355us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.680s 216.801us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 1.890s 65.302us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 4.850s 121.036us 1 1 100.00
keymgr_csr_rw 0.780s 39.100us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 4.850s 121.036us 1 1 100.00
keymgr_csr_rw 0.780s 39.100us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 4.850s 121.036us 1 1 100.00
keymgr_csr_rw 0.780s 39.100us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 3.620s 716.145us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.420s 236.687us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.420s 236.687us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.850s 121.036us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.980s 433.544us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.580s 88.838us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 3.620s 716.145us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.580s 88.838us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.580s 88.838us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.580s 88.838us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.080s 441.941us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.580s 88.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 4.950s 406.311us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 88410428848665939295591702151596247235945725263054336434078900871188481404194 833
UVM_ERROR @ 406311203 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 406311203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---