Simulation Results: kmac/masked

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.49 %
  • code
  • 89.23 %
  • assert
  • 97.98 %
  • func
  • 93.27 %
  • line
  • 98.40 %
  • branch
  • 95.39 %
  • cond
  • 90.93 %
  • toggle
  • 99.46 %
  • FSM
  • 61.97 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 51.310s 3184.628us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.140s 54.259us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.030s 16.925us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 6.640s 520.130us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.820s 166.790us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.740s 41.987us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.030s 16.925us 1 1 100.00
kmac_csr_aliasing 5.820s 166.790us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.810s 20.011us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.310s 55.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 511.210s 46896.306us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 247.740s 6779.326us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 28.800s 9134.940us 1 1 100.00
kmac_test_vectors_sha3_256 28.620s 3082.742us 1 1 100.00
kmac_test_vectors_sha3_384 22.360s 1747.404us 1 1 100.00
kmac_test_vectors_sha3_512 11.470s 665.125us 1 1 100.00
kmac_test_vectors_shake_128 2139.680s 72264.948us 1 1 100.00
kmac_test_vectors_shake_256 294.380s 18599.798us 1 1 100.00
kmac_test_vectors_kmac 2.750s 126.325us 1 1 100.00
kmac_test_vectors_kmac_xof 2.490s 148.192us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 206.450s 4024.714us 1 1 100.00
app 1 1 100.00
kmac_app 153.640s 9407.577us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 137.390s 54441.855us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 13.850s 787.697us 1 1 100.00
error 1 1 100.00
kmac_error 98.290s 21294.370us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 10.070s 1370.353us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 1.530s 75.137us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 22.780s 1963.689us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 27.910s 2389.327us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 48.960s 54962.197us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.760s 754.421us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 2152.380s 147406.252us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.800s 29.035us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.840s 54.058us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.740s 63.654us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.740s 63.654us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.140s 54.259us 1 1 100.00
kmac_csr_rw 1.030s 16.925us 1 1 100.00
kmac_csr_aliasing 5.820s 166.790us 1 1 100.00
kmac_same_csr_outstanding 1.280s 415.336us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.140s 54.259us 1 1 100.00
kmac_csr_rw 1.030s 16.925us 1 1 100.00
kmac_csr_aliasing 5.820s 166.790us 1 1 100.00
kmac_same_csr_outstanding 1.280s 415.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.760s 312.045us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.760s 312.045us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.760s 312.045us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.760s 312.045us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.330s 261.723us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 2.350s 111.157us 1 1 100.00
kmac_sec_cm 63.270s 26584.556us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.350s 111.157us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.760s 754.421us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 51.310s 3184.628us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 206.450s 4024.714us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.760s 312.045us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 63.270s 26584.556us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 63.270s 26584.556us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 63.270s 26584.556us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 51.310s 3184.628us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.760s 754.421us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 63.270s 26584.556us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 114.090s 24877.021us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 51.310s 3184.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 5.230s 2412.677us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 91252418048717385696664916833887271249837313972365778181862744419848362619291 190
UVM_ERROR @ 2412677238 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 2412677238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---