Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.57 %
  • code
  • 82.23 %
  • assert
  • 94.13 %
  • func
  • 92.35 %
  • line
  • 97.08 %
  • branch
  • 93.51 %
  • cond
  • 78.81 %
  • toggle
  • 81.94 %
  • FSM
  • 59.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.490s 226.842us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.870s 100.620us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.810s 23.718us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.110s 20.600us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 76.493us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.180s 56.290us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.810s 23.718us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 76.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.650s 66.549us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.250s 1357.947us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.700s 41.765us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.800s 155.765us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.250s 264.430us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_ctrl_prog_failure 1.800s 155.765us 1 1 100.00
lc_ctrl_errors 6.250s 264.430us 1 1 100.00
lc_ctrl_security_escalation 6.550s 233.426us 1 1 100.00
lc_ctrl_jtag_state_failure 24.400s 1061.653us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.190s 863.604us 1 1 100.00
lc_ctrl_jtag_errors 27.290s 14273.350us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 2.050s 344.431us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.230s 478.410us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.040s 1322.513us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 15.440s 4144.901us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.030s 85.203us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.100s 218.177us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 104.495us 1 1 100.00
lc_ctrl_jtag_smoke 4.390s 199.097us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.200s 804.713us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.190s 863.604us 1 1 100.00
lc_ctrl_jtag_errors 27.290s 14273.350us 1 1 100.00
lc_ctrl_jtag_access 8.370s 2851.630us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 27.790s 1359.523us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.410s 544.539us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.840s 163.065us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 110.740s 7993.720us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.930s 83.678us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.350s 37.353us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.350s 37.353us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 100.620us 1 1 100.00
lc_ctrl_csr_rw 0.810s 23.718us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 76.493us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 208.281us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 100.620us 1 1 100.00
lc_ctrl_csr_rw 0.810s 23.718us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 76.493us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 208.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.360s 131.795us 1 1 100.00
lc_ctrl_sec_cm 6.420s 131.653us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.360s 131.795us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.250s 1357.947us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_ctrl_sec_cm 6.420s 131.653us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_ctrl_sec_cm 6.420s 131.653us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_ctrl_sec_cm 6.420s 131.653us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_ctrl_sec_cm 6.420s 131.653us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_ctrl_sec_cm 6.420s 131.653us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_ctrl_sec_cm 6.420s 131.653us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_ctrl_sec_cm 6.420s 131.653us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.060s 281.990us 1 1 100.00
lc_ctrl_sec_cm 6.420s 131.653us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.550s 233.426us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.650s 66.549us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.200s 804.713us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.220s 5365.877us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.220s 5365.877us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.580s 1948.722us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.040s 355.447us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.040s 355.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 32.400s 3160.997us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 55368320201567440669978565848227520041351093131028409018260795018999312066781 1376
UVM_ERROR @ 3160997434 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3160997434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---