Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.01 %
  • code
  • 84.41 %
  • assert
  • 94.13 %
  • func
  • 94.48 %
  • line
  • 97.10 %
  • branch
  • 93.77 %
  • cond
  • 79.28 %
  • toggle
  • 87.39 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.540s 31.038us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.120s 73.549us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.820s 28.523us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.380s 41.216us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.320s 34.599us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.010s 21.490us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.820s 28.523us 1 1 100.00
lc_ctrl_csr_aliasing 1.320s 34.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.190s 75.850us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.040s 332.191us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.920s 12.883us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.240s 216.143us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.180s 277.961us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_ctrl_prog_failure 2.240s 216.143us 1 1 100.00
lc_ctrl_errors 5.180s 277.961us 1 1 100.00
lc_ctrl_security_escalation 7.070s 632.190us 1 1 100.00
lc_ctrl_jtag_state_failure 20.250s 17890.191us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.300s 1575.723us 1 1 100.00
lc_ctrl_jtag_errors 20.440s 7716.166us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.540s 47.735us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.100s 70.395us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.690s 476.436us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 12.360s 1472.828us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.130s 41.967us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.660s 85.850us 1 1 100.00
lc_ctrl_jtag_alert_test 1.730s 145.792us 1 1 100.00
lc_ctrl_jtag_smoke 4.290s 919.033us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.710s 3301.151us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.300s 1575.723us 1 1 100.00
lc_ctrl_jtag_errors 20.440s 7716.166us 1 1 100.00
lc_ctrl_jtag_access 4.220s 525.228us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.330s 17368.517us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 12.830s 1205.466us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 46.034us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 84.560s 4226.870us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.710s 58.952us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.240s 57.734us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.240s 57.734us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.120s 73.549us 1 1 100.00
lc_ctrl_csr_rw 0.820s 28.523us 1 1 100.00
lc_ctrl_csr_aliasing 1.320s 34.599us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 26.604us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.120s 73.549us 1 1 100.00
lc_ctrl_csr_rw 0.820s 28.523us 1 1 100.00
lc_ctrl_csr_aliasing 1.320s 34.599us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 26.604us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 2.210s 103.922us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1070.901us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.210s 103.922us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.040s 332.191us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1070.901us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1070.901us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1070.901us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1070.901us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1070.901us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1070.901us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1070.901us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 10.200s 2841.306us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1070.901us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.070s 632.190us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.190s 75.850us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.710s 3301.151us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.020s 817.581us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.020s 817.581us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.700s 498.748us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.560s 6870.286us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.560s 6870.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 68.920s 23756.552us 1 1 100.00