Simulation Results: pwrmgr

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.34 %
  • code
  • 89.85 %
  • assert
  • 95.82 %
  • func
  • 97.36 %
  • line
  • 98.76 %
  • branch
  • 94.85 %
  • cond
  • 93.64 %
  • toggle
  • 90.02 %
  • FSM
  • 72.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
70.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.630s 119.100us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.630s 33.997us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.610s 38.994us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.940s 137.092us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.750s 127.947us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.030s 53.649us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.610s 38.994us 1 1 100.00
pwrmgr_csr_aliasing 0.750s 127.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.970s 275.793us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.970s 275.793us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.770s 96.692us 1 1 100.00
pwrmgr_lowpower_invalid 0.670s 53.213us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.810s 103.050us 1 1 100.00
pwrmgr_reset_invalid 0.670s 42.706us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.810s 103.050us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.740s 79.625us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.950s 376.269us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.800s 133.071us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 17.080s 10623.808us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.640s 18.885us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.850s 401.943us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.850s 401.943us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 33.997us 1 1 100.00
pwrmgr_csr_rw 0.610s 38.994us 1 1 100.00
pwrmgr_csr_aliasing 0.750s 127.947us 1 1 100.00
pwrmgr_same_csr_outstanding 0.710s 28.792us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 33.997us 1 1 100.00
pwrmgr_csr_rw 0.610s 38.994us 1 1 100.00
pwrmgr_csr_aliasing 0.750s 127.947us 1 1 100.00
pwrmgr_same_csr_outstanding 0.710s 28.792us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.770s 32.720us 0 1 0.00
pwrmgr_tl_intg_err 0.750s 7.148us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.770s 32.720us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.770s 32.720us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.750s 7.148us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.970s 719.907us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.740s 79.625us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.790s 234.000us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 0 1 0.00
pwrmgr_esc_clk_rst_malfunc 0.550s 14.086us 0 1 0.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.770s 32.720us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.770s 32.720us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.770s 32.720us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.630s 47.895us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.610s 49.637us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.750s 187.923us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.610s 38.994us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.610s 38.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.730s 340.590us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 9.990s 13185.497us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
pwrmgr_esc_clk_rst_malfunc 74370899807976558599535319046296424804824787486020854769123924132249771974011 75
UVM_ERROR @ 14086499 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 14086499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 87101683233069219009482063863102027700134518868298998937749079637735006964271 75
UVM_ERROR @ 340589819 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 340589819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitResetPrep
pwrmgr_reset_invalid 38735269428544411176394946180368397449341459296034588236456531367945817897941 116
UVM_FATAL @ 42706285 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitResetPrep
UVM_INFO @ 42706285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_sec_cm 35145551309083996955820555296383069223424772541870004140233334467615230591203 85
UVM_ERROR @ 32720475 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 32720475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 33517301906088834853965788170071835904131825254641454974549506034406037206070 82
UVM_ERROR @ 7148120 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 7148120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
pwrmgr_stress_all 14191946967932031888030402385604210553272818797429149990597130678744750270393 598
UVM_FATAL @ 10623807740 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred!
UVM_INFO @ 10623807740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---