Simulation Results: rom_ctrl/32kb

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.66 %
  • code
  • 98.10 %
  • assert
  • 96.80 %
  • func
  • 98.09 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.51 %
  • toggle
  • 99.95 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.680s 544.785us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.320s 187.652us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.340s 171.773us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.630s 2097.083us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.280s 538.431us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.130s 176.608us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.340s 171.773us 1 1 100.00
rom_ctrl_csr_aliasing 4.280s 538.431us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.850s 567.801us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.400s 993.851us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.490s 195.347us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.250s 2594.839us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.330s 1042.878us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.650s 366.929us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.510s 728.514us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.510s 728.514us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.320s 187.652us 1 1 100.00
rom_ctrl_csr_rw 4.340s 171.773us 1 1 100.00
rom_ctrl_csr_aliasing 4.280s 538.431us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.650s 1852.759us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.320s 187.652us 1 1 100.00
rom_ctrl_csr_rw 4.340s 171.773us 1 1 100.00
rom_ctrl_csr_aliasing 4.280s 538.431us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.650s 1852.759us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.820s 656.262us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_tl_intg_err 41.270s 871.127us 1 1 100.00
rom_ctrl_sec_cm 192.900s 2038.167us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 192.900s 2038.167us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 192.900s 2038.167us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 192.900s 2038.167us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 192.900s 2038.167us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.680s 544.785us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.680s 544.785us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.680s 544.785us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 41.270s 871.127us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
rom_ctrl_kmac_err_chk 7.330s 1042.878us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 45.150s 3889.246us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.820s 656.262us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 192.900s 2038.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 171.680s 8081.303us 1 1 100.00