Simulation Results: rom_ctrl/64kb

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.33 %
  • code
  • 96.51 %
  • assert
  • 96.80 %
  • func
  • 80.67 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.33 %
  • toggle
  • 99.80 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.660s 314.316us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.250s 1082.008us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.780s 545.566us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.520s 1072.887us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 9.970s 1041.928us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.850s 1278.671us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.780s 545.566us 1 1 100.00
rom_ctrl_csr_aliasing 9.970s 1041.928us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.970s 1577.210us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.800s 391.259us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.650s 737.569us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 28.150s 2760.105us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 11.870s 4765.272us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.820s 3549.781us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.130s 212.748us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.130s 212.748us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.250s 1082.008us 1 1 100.00
rom_ctrl_csr_rw 6.780s 545.566us 1 1 100.00
rom_ctrl_csr_aliasing 9.970s 1041.928us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.660s 3161.178us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.250s 1082.008us 1 1 100.00
rom_ctrl_csr_rw 6.780s 545.566us 1 1 100.00
rom_ctrl_csr_aliasing 9.970s 1041.928us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.660s 3161.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.850s 4073.875us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_tl_intg_err 95.370s 3888.868us 1 1 100.00
rom_ctrl_sec_cm 460.310s 1719.476us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 460.310s 1719.476us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 460.310s 1719.476us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 460.310s 1719.476us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 460.310s 1719.476us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.660s 314.316us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.660s 314.316us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.660s 314.316us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 95.370s 3888.868us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
rom_ctrl_kmac_err_chk 11.870s 4765.272us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 86.000s 2629.139us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.850s 4073.875us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 460.310s 1719.476us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 9.120s 386.322us 1 1 100.00