Simulation Results: rstmgr

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.29 %
  • code
  • 99.35 %
  • assert
  • 97.99 %
  • func
  • 94.53 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 99.25 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.120s 125.538us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.840s 142.774us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.910s 92.493us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.760s 1566.010us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.290s 211.036us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.310s 185.706us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.910s 92.493us 1 1 100.00
rstmgr_csr_aliasing 1.290s 211.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.800s 216.911us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.660s 360.362us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.790s 93.833us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 2.870s 791.293us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 2.870s 791.293us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 2.870s 791.293us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 2.870s 791.293us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 5.350s 1941.848us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.710s 72.566us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.270s 201.828us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.270s 201.828us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.840s 142.774us 1 1 100.00
rstmgr_csr_rw 0.910s 92.493us 1 1 100.00
rstmgr_csr_aliasing 1.290s 211.036us 1 1 100.00
rstmgr_same_csr_outstanding 1.180s 202.458us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.840s 142.774us 1 1 100.00
rstmgr_csr_rw 0.910s 92.493us 1 1 100.00
rstmgr_csr_aliasing 1.290s 211.036us 1 1 100.00
rstmgr_same_csr_outstanding 1.180s 202.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.110s 8738.731us 1 1 100.00
rstmgr_tl_intg_err 2.390s 935.964us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.110s 8738.731us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.110s 8738.731us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.390s 935.964us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.090s 169.456us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.520s 1271.867us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.090s 301.524us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.110s 8738.731us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.910s 92.493us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.910s 92.493us 1 1 100.00