Simulation Results: rv_timer

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.98 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 94.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.860s 599.895us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.670s 44.926us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.630s 14.932us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.240s 255.670us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.850s 118.381us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.980s 84.962us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.630s 14.932us 1 1 100.00
rv_timer_csr_aliasing 0.850s 118.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.590s 1095.562us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.960s 701.770us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 39.270s 102463.923us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 39.270s 102463.923us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.780s 16.950us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.670s 32.342us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.580s 12.799us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.280s 226.185us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.280s 226.185us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 44.926us 1 1 100.00
rv_timer_csr_rw 0.630s 14.932us 1 1 100.00
rv_timer_csr_aliasing 0.850s 118.381us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 29.303us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 44.926us 1 1 100.00
rv_timer_csr_rw 0.630s 14.932us 1 1 100.00
rv_timer_csr_aliasing 0.850s 118.381us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 29.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.180s 372.432us 1 1 100.00
rv_timer_tl_intg_err 1.030s 347.790us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.030s 347.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.940s 117.316us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.840s 92.677us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 23.980s 16771.951us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 70542562020394687948458330750351206298443673391900199646684699524235932208682 75
UVM_FATAL @ 117315603 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8700dd04) == 0x1
UVM_INFO @ 117315603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 62669239329228796633241960453287581956216371174469193018157062338249892362299 77
UVM_FATAL @ 1095561662 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x18276904) == 0x1
UVM_INFO @ 1095561662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 75218295937882343718596971028568002511889916618317579992450538510169603078326 75
UVM_ERROR @ 92677078 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 92677078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---