Simulation Results

Simulation Results: spi_device/1r1w

06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.09 %

code
93.26 %

assert
94.39 %

func
67.61 %

line
99.03 %

branch
98.27 %

cond
96.08 %

toggle
83.54 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		92.31%
V2S		100.00%
unmapped		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	64.360s	10700.323us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	1.070s	21.525us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.360s	881.612us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	9.150s	1242.949us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	15.600s	3620.501us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	1.350s	42.436us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.360s	881.612us	1	1	100.00
	spi_device_csr_aliasing	15.600s	3620.501us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.780s	39.356us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.710s	61.602us	1	1	100.00

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.860s	20.395us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.790s	1.504us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.660s	3.479us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	2.000s	98.838us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	2.000s	98.838us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	1.270s	500.323us	1	1	100.00
	spi_device_tpm_sts_read	0.820s	34.900us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	21.820s	12592.911us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	2.430s	300.809us	1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	4.720s	4715.128us	1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	4.720s	4715.128us	1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	3.800s	1103.433us	1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	3.800s	1103.433us	1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	3.800s	1103.433us	1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	3.800s	1103.433us	1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	3.800s	1103.433us	1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	2.250s	131.618us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	53.770s	34639.151us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	53.770s	34639.151us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	53.770s	34639.151us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	10.570s	1048.230us	1	1	100.00
	spi_device_read_buffer_direct	4.470s	444.671us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	53.770s	34639.151us	1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	130.290s	29340.354us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	2.450s	814.589us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	2.450s	814.589us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	64.360s	10700.323us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	55.500s	10224.379us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	19.140s	2037.208us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.740s	41.619us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.760s	16.283us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	3.160s	70.733us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	3.160s	70.733us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	1.070s	21.525us	1	1	100.00
	spi_device_csr_rw	1.360s	881.612us	1	1	100.00
	spi_device_csr_aliasing	15.600s	3620.501us	1	1	100.00
	spi_device_same_csr_outstanding	2.900s	349.125us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	1.070s	21.525us	1	1	100.00
	spi_device_csr_rw	1.360s	881.612us	1	1	100.00
	spi_device_csr_aliasing	15.600s	3620.501us	1	1	100.00
	spi_device_same_csr_outstanding	2.900s	349.125us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	5.760s	271.630us	1	1	100.00
	spi_device_sec_cm	1.290s	97.666us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	5.760s	271.630us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	51.080s	10225.235us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	43520994393313574759183966241314701126753224156192916933229594551391155600566	76	UVM_ERROR @ 1129096 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[37]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 1129096 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 1129096 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[933]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	41041138517381116718828062331994772069972505061522014199117109604433648014855	76	UVM_ERROR @ 748988 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xba4a4 [10111010010010100100] vs 0x0 [0]) UVM_ERROR @ 775988 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8a602c [100010100110000000101100] vs 0x0 [0]) UVM_ERROR @ 840988 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x41af6 [1000001101011110110] vs 0x0 [0]) UVM_ERROR @ 848988 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8c650c [100011000110010100001100] vs 0x0 [0]) UVM_ERROR @ 890988 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcd7bd2 [110011010111101111010010] vs 0x0 [0])