Simulation Results: spi_device/2p

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.43 %
  • code
  • 93.90 %
  • assert
  • 94.62 %
  • func
  • 61.76 %
  • line
  • 99.06 %
  • branch
  • 98.26 %
  • cond
  • 95.41 %
  • toggle
  • 87.39 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 30.920s 6729.558us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.080s 36.553us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.580s 76.015us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.840s 3097.192us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.110s 439.642us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.320s 228.523us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.580s 76.015us 1 1 100.00
spi_device_csr_aliasing 10.110s 439.642us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.660s 15.805us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.330s 24.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.730s 75.471us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.980s 97.665us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.730s 35.219us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.760s 906.065us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.760s 906.065us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.340s 3918.939us 1 1 100.00
spi_device_tpm_sts_read 0.970s 76.340us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 2.860s 906.562us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.010s 2781.607us 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 14.120s 15150.686us 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 14.120s 15150.686us 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 9.980s 12533.971us 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 9.980s 12533.971us 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 9.980s 12533.971us 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 9.980s 12533.971us 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 9.980s 12533.971us 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 9.690s 19026.315us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 77.390s 47644.358us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 77.390s 47644.358us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 77.390s 47644.358us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.740s 522.872us 1 1 100.00
spi_device_read_buffer_direct 2.610s 108.595us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 77.390s 47644.358us 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 20.220s 7424.659us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.170s 105.653us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.170s 105.653us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 30.920s 6729.558us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 113.160s 44931.473us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 103.160s 17783.932us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.800s 11.389us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.730s 116.642us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.560s 30.901us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.560s 30.901us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.080s 36.553us 1 1 100.00
spi_device_csr_rw 1.580s 76.015us 1 1 100.00
spi_device_csr_aliasing 10.110s 439.642us 1 1 100.00
spi_device_same_csr_outstanding 3.080s 649.993us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.080s 36.553us 1 1 100.00
spi_device_csr_rw 1.580s 76.015us 1 1 100.00
spi_device_csr_aliasing 10.110s 439.642us 1 1 100.00
spi_device_same_csr_outstanding 3.080s 649.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 4.810s 104.089us 1 1 100.00
spi_device_sec_cm 1.040s 98.629us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 4.810s 104.089us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 27.560s 12629.176us 1 1 100.00