Simulation Results: spi_host

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.75 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 18.000s 1579.790us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 17.422us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 17.861us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 1353.659us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 109.348us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 62.573us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 17.861us 1 1 100.00
spi_host_csr_aliasing 1.000s 109.348us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.353us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 19.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 40.433us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 41.594us 1 1 100.00
spi_host_error_cmd 1.000s 17.724us 1 1 100.00
spi_host_event 5.000s 3250.027us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 38.085us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 38.085us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 38.085us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 167.000s 7944.705us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 71.303us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 38.085us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 38.085us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 18.000s 1579.790us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 18.000s 1579.790us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 32.000s 1797.324us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 3032.661us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 19.000s 2811.196us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 249.503us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 41.594us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 46.455us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 25.555us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 218.787us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 218.787us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.422us 1 1 100.00
spi_host_csr_rw 1.000s 17.861us 1 1 100.00
spi_host_csr_aliasing 1.000s 109.348us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 93.886us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.422us 1 1 100.00
spi_host_csr_rw 1.000s 17.861us 1 1 100.00
spi_host_csr_aliasing 1.000s 109.348us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 93.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 283.393us 1 1 100.00
spi_host_tl_intg_err 2.000s 101.801us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 101.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 234.000s 11724.701us 1 1 100.00