Simulation Results: sram_ctrl/main

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.90 %
  • code
  • 87.98 %
  • assert
  • 95.55 %
  • func
  • 95.18 %
  • line
  • 96.96 %
  • branch
  • 94.31 %
  • cond
  • 91.31 %
  • toggle
  • 90.65 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 10.200s 8319.442us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.720s 14.458us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.760s 175.032us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.240s 361.182us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.800s 18.848us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.380s 1220.811us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.760s 175.032us 1 1 100.00
sram_ctrl_csr_aliasing 0.800s 18.848us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 109.750s 10518.633us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 116.550s 10381.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 780.690s 26220.537us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 75.770s 1632.537us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1269.840s 48860.303us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 391.470s 11472.687us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 53.360s 57211.684us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 688.530s 22218.017us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 15.640s 5862.373us 1 1 100.00
sram_ctrl_partial_access_b2b 323.830s 64870.491us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 19.700s 2906.069us 1 1 100.00
sram_ctrl_throughput_w_partial_write 33.400s 798.658us 1 1 100.00
sram_ctrl_throughput_w_readback 41.030s 1732.516us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 537.110s 26420.394us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.270s 343.978us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1915.220s 81648.970us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.860s 44.243us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.190s 260.360us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.190s 260.360us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.720s 14.458us 1 1 100.00
sram_ctrl_csr_rw 0.760s 175.032us 1 1 100.00
sram_ctrl_csr_aliasing 0.800s 18.848us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.730s 16.232us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.720s 14.458us 1 1 100.00
sram_ctrl_csr_rw 0.760s 175.032us 1 1 100.00
sram_ctrl_csr_aliasing 0.800s 18.848us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.730s 16.232us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.560s 14890.198us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.780s 658.110us 1 1 100.00
sram_ctrl_sec_cm 0.840s 14.155us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.840s 14.155us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.780s 658.110us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 537.110s 26420.394us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 537.110s 26420.394us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.760s 175.032us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 688.530s 22218.017us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 688.530s 22218.017us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 688.530s 22218.017us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 53.360s 57211.684us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3.810s 685.496us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.560s 14890.198us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.290s 1351.269us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 10.200s 8319.442us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 10.200s 8319.442us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 688.530s 22218.017us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.840s 14.155us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 53.360s 57211.684us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.840s 14.155us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.840s 14.155us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 10.200s 8319.442us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.840s 14.155us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 16.220s 3378.383us 1 1 100.00

Error Messages

   Test seed line log context
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 87021452170340377879049038029515166075333270672599268145477689385150584773187 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 685496113 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 685496113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 86823021572516799427102937891897669519266297891244652637812280459534157398433 101
UVM_ERROR @ 14155167 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 14155167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---