Simulation Results: sram_ctrl/ret

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.44 %
  • code
  • 93.68 %
  • assert
  • 95.79 %
  • func
  • 96.85 %
  • line
  • 98.51 %
  • branch
  • 96.46 %
  • cond
  • 92.29 %
  • toggle
  • 90.66 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.870s 116.849us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.700s 19.446us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.680s 33.345us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.590s 43.512us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 15.218us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.050s 38.216us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.680s 33.345us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 15.218us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.500s 2388.267us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.360s 62.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 929.510s 39626.226us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 261.220s 7642.326us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 57.170s 3878.687us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 203.340s 6634.491us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.480s 580.344us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 809.530s 19560.095us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 12.810s 1807.865us 1 1 100.00
sram_ctrl_partial_access_b2b 316.820s 26270.423us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 18.020s 99.185us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.770s 638.449us 1 1 100.00
sram_ctrl_throughput_w_readback 5.570s 191.973us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 528.610s 2457.647us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.880s 34.911us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1918.050s 29756.107us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.800s 26.932us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.750s 339.733us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.750s 339.733us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.700s 19.446us 1 1 100.00
sram_ctrl_csr_rw 0.680s 33.345us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 15.218us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.970s 45.173us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.700s 19.446us 1 1 100.00
sram_ctrl_csr_rw 0.680s 33.345us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 15.218us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.970s 45.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.280s 403.648us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.920s 830.045us 1 1 100.00
sram_ctrl_sec_cm 0.720s 3.624us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.720s 3.624us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.920s 830.045us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 528.610s 2457.647us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 528.610s 2457.647us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.680s 33.345us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 809.530s 19560.095us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 809.530s 19560.095us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 809.530s 19560.095us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.480s 580.344us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.340s 34.551us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.280s 403.648us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.220s 302.644us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.870s 116.849us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.870s 116.849us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 809.530s 19560.095us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.720s 3.624us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.480s 580.344us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.720s 3.624us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.720s 3.624us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.870s 116.849us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.720s 3.624us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 67.590s 9762.884us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 19565914770120108543265029878213216423015994908730185996536541811813842467728 100
UVM_ERROR @ 3623940 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3623940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---