Simulation Results: sysrst_ctrl

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.09 %
  • code
  • 94.20 %
  • assert
  • 95.50 %
  • func
  • 68.56 %
  • line
  • 98.10 %
  • branch
  • 97.92 %
  • cond
  • 95.51 %
  • toggle
  • 100.00 %
  • FSM
  • 79.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.850s 2130.130us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.850s 2439.557us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.740s 2414.373us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.310s 2580.574us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 11.620s 6038.041us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.740s 2083.665us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 43.860s 39127.831us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.060s 2588.838us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.540s 2118.161us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.740s 2083.665us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.060s 2588.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 35.150s 137158.007us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 12.440s 78681.673us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.190s 3553.372us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.090s 2488.690us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.540s 2523.488us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.860s 2235.195us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 7.670s 3816.014us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.080s 2618.592us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 5.330s 6516.854us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 8.500s 41664.408us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 5.830s 8859.372us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.360s 2012.516us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.740s 2036.646us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.520s 2037.955us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.520s 2037.955us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.620s 6038.041us 1 1 100.00
sysrst_ctrl_csr_rw 2.740s 2083.665us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.060s 2588.838us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.610s 4853.646us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.620s 6038.041us 1 1 100.00
sysrst_ctrl_csr_rw 2.740s 2083.665us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.060s 2588.838us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.610s 4853.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 6.180s 23074.080us 1 1 100.00
sysrst_ctrl_sec_cm 73.420s 42011.195us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 6.180s 23074.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 7.500s 5273.769us 1 1 100.00