Simulation Results: uart

 
06/04/2026 19:24:38 DVSim: v1.17.3 sha: d2f24af json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.82 %
  • code
  • 95.73 %
  • assert
  • 97.12 %
  • func
  • 52.61 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 95.22 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.990s 505.847us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.940s 1033.484us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.690s 13.473us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.260s 65.081us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.780s 30.575us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.950s 63.984us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.690s 13.473us 1 1 100.00
uart_csr_aliasing 0.780s 30.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 34.330s 39331.955us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.990s 505.847us 1 1 100.00
uart_tx_rx 34.330s 39331.955us 1 1 100.00
parity_error 2 2 100.00
uart_intr 17.130s 13173.453us 1 1 100.00
uart_rx_parity_err 31.390s 99035.532us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 34.330s 39331.955us 1 1 100.00
uart_intr 17.130s 13173.453us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 201.720s 273205.645us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 12.690s 13017.416us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 17.130s 50826.896us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 17.130s 13173.453us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 17.130s 13173.453us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 17.130s 13173.453us 1 1 100.00
perf 1 1 100.00
uart_perf 124.430s 14872.576us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.380s 2658.605us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.380s 2658.605us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 11.980s 24014.151us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.070s 3393.019us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.540s 930.253us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 28.130s 4520.967us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 115.370s 124239.500us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 230.270s 319391.425us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.550s 16.874us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 25.464us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.310s 263.764us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.310s 263.764us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.940s 1033.484us 1 1 100.00
uart_csr_rw 0.690s 13.473us 1 1 100.00
uart_csr_aliasing 0.780s 30.575us 1 1 100.00
uart_same_csr_outstanding 0.740s 53.226us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.940s 1033.484us 1 1 100.00
uart_csr_rw 0.690s 13.473us 1 1 100.00
uart_csr_aliasing 0.780s 30.575us 1 1 100.00
uart_same_csr_outstanding 0.740s 53.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 1.170s 651.664us 1 1 100.00
uart_sec_cm 1.140s 87.271us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.170s 651.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 21.450s 10575.469us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *
uart_noise_filter 31112647280935665220602159780122902512791254044857137083603603052706177586234 76
UVM_ERROR @ 21600230936 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 21662890936 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 21662930936 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (165 [0xa5] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 21662950936 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 21810410936 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0