Simulation Results: adc_ctrl

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.27 %
  • code
  • 96.85 %
  • assert
  • 95.46 %
  • func
  • 18.49 %
  • line
  • 99.05 %
  • branch
  • 97.71 %
  • cond
  • 92.89 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 6.650s 5796.092us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.820s 1261.417us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.870s 509.043us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 58.620s 41255.495us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.300s 652.881us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.240s 479.412us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.870s 509.043us 1 1 100.00
adc_ctrl_csr_aliasing 3.300s 652.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 132.730s 325490.578us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 286.130s 164860.520us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 141.520s 492419.509us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 128.010s 330748.396us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 92.370s 210164.488us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 517.080s 596658.743us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 673.460s 397205.523us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 208.430s 2000000.000us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 9.620s 4206.036us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 25.460s 30418.305us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 192.110s 117603.141us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 17.800s 69585.517us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.240s 327.306us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.030s 427.889us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.710s 422.319us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.710s 422.319us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.820s 1261.417us 1 1 100.00
adc_ctrl_csr_rw 0.870s 509.043us 1 1 100.00
adc_ctrl_csr_aliasing 3.300s 652.881us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.140s 2312.581us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.820s 1261.417us 1 1 100.00
adc_ctrl_csr_rw 0.870s 509.043us 1 1 100.00
adc_ctrl_csr_aliasing 3.300s 652.881us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.140s 2312.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 10.030s 3942.120us 1 1 100.00
adc_ctrl_tl_intg_err 4.980s 4289.104us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.980s 4289.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 6.390s 10655.262us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 54748129311534456328998516803886727589158646666432153363430954407223763554821 342
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---