Simulation Results: aes/masked

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.44 %
  • code
  • 95.08 %
  • assert
  • 98.43 %
  • func
  • 68.81 %
  • block
  • 95.68 %
  • line
  • 97.44 %
  • branch
  • 89.34 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 77.379us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 138.779us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 71.622us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 65.718us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 331.431us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 527.003us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 90.726us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 65.718us 1 1 100.00
aes_csr_aliasing 3.000s 527.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 138.779us 1 1 100.00
aes_config_error 4.000s 114.008us 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 138.779us 1 1 100.00
aes_config_error 4.000s 114.008us 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 129.171us 1 1 100.00
aes_b2b 8.000s 253.181us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 138.779us 1 1 100.00
aes_config_error 4.000s 114.008us 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
aes_alert_reset 4.000s 166.750us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 53.025us 1 1 100.00
aes_config_error 4.000s 114.008us 1 1 100.00
aes_alert_reset 4.000s 166.750us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 255.384us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 543.766us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 378.723us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 166.750us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 129.171us 1 1 100.00
aes_sideload 3.000s 229.012us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 74.466us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 14.000s 1691.851us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 66.001us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 81.580us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 122.151us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 122.151us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 71.622us 1 1 100.00
aes_csr_rw 2.000s 65.718us 1 1 100.00
aes_csr_aliasing 3.000s 527.003us 1 1 100.00
aes_same_csr_outstanding 1.000s 60.848us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 71.622us 1 1 100.00
aes_csr_rw 2.000s 65.718us 1 1 100.00
aes_csr_aliasing 3.000s 527.003us 1 1 100.00
aes_same_csr_outstanding 1.000s 60.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 8.000s 149.288us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 1476.524us 1 1 100.00
aes_control_fi 3.000s 56.446us 1 1 100.00
aes_cipher_fi 17.000s 10017.225us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 156.149us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 156.149us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 156.149us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 156.149us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 201.168us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 3.000s 192.810us 1 1 100.00
aes_sec_cm 4.000s 1107.502us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 192.810us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 166.750us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 156.149us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 156.149us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 138.779us 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
aes_alert_reset 4.000s 166.750us 1 1 100.00
aes_core_fi 2.000s 153.354us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 66.001us 1 1 100.00
aes_config_error 4.000s 114.008us 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
aes_core_fi 2.000s 153.354us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 156.149us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 78.988us 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 129.171us 1 1 100.00
aes_sideload 3.000s 229.012us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 78.988us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 78.988us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 78.988us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 78.988us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 78.988us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 129.171us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 1476.524us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 1476.524us 1 1 100.00
aes_control_fi 3.000s 56.446us 1 1 100.00
aes_cipher_fi 17.000s 10017.225us 0 1 0.00
aes_ctr_fi 2.000s 55.664us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 1476.524us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 1476.524us 1 1 100.00
aes_control_fi 3.000s 56.446us 1 1 100.00
aes_cipher_fi 17.000s 10017.225us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 17.000s 10017.225us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 1476.524us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 4.000s 1476.524us 1 1 100.00
aes_control_fi 3.000s 56.446us 1 1 100.00
aes_ctr_fi 2.000s 55.664us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 4.000s 1476.524us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 1476.524us 1 1 100.00
aes_control_fi 3.000s 56.446us 1 1 100.00
aes_cipher_fi 17.000s 10017.225us 0 1 0.00
aes_ctr_fi 2.000s 55.664us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 166.750us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 1476.524us 1 1 100.00
aes_control_fi 3.000s 56.446us 1 1 100.00
aes_cipher_fi 17.000s 10017.225us 0 1 0.00
aes_ctr_fi 2.000s 55.664us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 1476.524us 1 1 100.00
aes_control_fi 3.000s 56.446us 1 1 100.00
aes_cipher_fi 17.000s 10017.225us 0 1 0.00
aes_ctr_fi 2.000s 55.664us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 4.000s 1476.524us 1 1 100.00
aes_control_fi 3.000s 56.446us 1 1 100.00
aes_ctr_fi 2.000s 55.664us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 4.000s 1476.524us 1 1 100.00
aes_ghash_fi 2.000s 56.934us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 1476.524us 1 1 100.00
aes_control_fi 3.000s 56.446us 1 1 100.00
aes_cipher_fi 17.000s 10017.225us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 956.347us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 62317341780946587838636020988609443303478962317159091014692845133362637975059 143
UVM_FATAL @ 10017224675 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10017224675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 106136352112795376063806214427683578657098002518220449730028558961594298152303 807
UVM_ERROR @ 956347100 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 956347100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---