Simulation Results: aes/unmasked

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.89 %
  • code
  • 91.25 %
  • assert
  • 97.75 %
  • func
  • 68.67 %
  • block
  • 90.69 %
  • line
  • 93.05 %
  • branch
  • 83.17 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 55.498us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 150.328us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 57.666us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 106.246us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 1559.201us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 303.385us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 86.510us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 106.246us 1 1 100.00
aes_csr_aliasing 2.000s 303.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 150.328us 1 1 100.00
aes_config_error 2.000s 349.592us 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 150.328us 1 1 100.00
aes_config_error 2.000s 349.592us 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 61.663us 1 1 100.00
aes_b2b 4.000s 183.058us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 150.328us 1 1 100.00
aes_config_error 2.000s 349.592us 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
aes_alert_reset 3.000s 112.413us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 72.307us 1 1 100.00
aes_config_error 2.000s 349.592us 1 1 100.00
aes_alert_reset 3.000s 112.413us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 86.691us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 839.326us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 5.000s 432.442us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 112.413us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 61.663us 1 1 100.00
aes_sideload 3.000s 70.807us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 91.619us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 13.000s 1015.630us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 118.884us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 58.246us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 7.000s 263.881us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 7.000s 263.881us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 57.666us 1 1 100.00
aes_csr_rw 2.000s 106.246us 1 1 100.00
aes_csr_aliasing 2.000s 303.385us 1 1 100.00
aes_same_csr_outstanding 2.000s 107.580us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 57.666us 1 1 100.00
aes_csr_rw 2.000s 106.246us 1 1 100.00
aes_csr_aliasing 2.000s 303.385us 1 1 100.00
aes_same_csr_outstanding 2.000s 107.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 84.078us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 2.000s 167.466us 1 1 100.00
aes_control_fi 19.000s 10006.612us 0 1 0.00
aes_cipher_fi 11.000s 10006.807us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 109.179us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 109.179us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 109.179us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 109.179us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 532.223us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 4.000s 284.598us 1 1 100.00
aes_sec_cm 4.000s 1168.885us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 284.598us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 112.413us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 109.179us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 109.179us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 150.328us 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
aes_alert_reset 3.000s 112.413us 1 1 100.00
aes_core_fi 2.000s 75.700us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 118.884us 1 1 100.00
aes_config_error 2.000s 349.592us 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
aes_core_fi 2.000s 75.700us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 109.179us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 66.570us 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 61.663us 1 1 100.00
aes_sideload 3.000s 70.807us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.570us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.570us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 66.570us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 66.570us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 66.570us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 61.663us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 167.466us 1 1 100.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 2.000s 167.466us 1 1 100.00
aes_control_fi 19.000s 10006.612us 0 1 0.00
aes_cipher_fi 11.000s 10006.807us 0 1 0.00
aes_ctr_fi 1.000s 57.209us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 167.466us 1 1 100.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 2.000s 167.466us 1 1 100.00
aes_control_fi 19.000s 10006.612us 0 1 0.00
aes_cipher_fi 11.000s 10006.807us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 11.000s 10006.807us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 167.466us 1 1 100.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 167.466us 1 1 100.00
aes_control_fi 19.000s 10006.612us 0 1 0.00
aes_ctr_fi 1.000s 57.209us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 2.000s 167.466us 1 1 100.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 2.000s 167.466us 1 1 100.00
aes_control_fi 19.000s 10006.612us 0 1 0.00
aes_cipher_fi 11.000s 10006.807us 0 1 0.00
aes_ctr_fi 1.000s 57.209us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 112.413us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 2.000s 167.466us 1 1 100.00
aes_control_fi 19.000s 10006.612us 0 1 0.00
aes_cipher_fi 11.000s 10006.807us 0 1 0.00
aes_ctr_fi 1.000s 57.209us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 2.000s 167.466us 1 1 100.00
aes_control_fi 19.000s 10006.612us 0 1 0.00
aes_cipher_fi 11.000s 10006.807us 0 1 0.00
aes_ctr_fi 1.000s 57.209us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 167.466us 1 1 100.00
aes_control_fi 19.000s 10006.612us 0 1 0.00
aes_ctr_fi 1.000s 57.209us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 2.000s 167.466us 1 1 100.00
aes_ghash_fi 2.000s 48.124us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 2.000s 167.466us 1 1 100.00
aes_control_fi 19.000s 10006.612us 0 1 0.00
aes_cipher_fi 11.000s 10006.807us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 593.003us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 61540861878067457360024278859753523298555096326971800812801574749347745685150 140
UVM_FATAL @ 10006611880 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006611880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 45804364871026754939759447547243701146065385883132964922870617324432999966325 144
UVM_FATAL @ 10006807478 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006807478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT
aes_stress_all_with_rand_reset 81922960129113907042625627490199355192370000911492715724269555751455462073909 307
UVM_FATAL @ 593003270 ps: (aes_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT
UVM_INFO @ 593003270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---