Simulation Results: alert_handler

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.42 %
  • code
  • 92.69 %
  • assert
  • 98.23 %
  • func
  • 80.34 %
  • line
  • 99.68 %
  • branch
  • 98.33 %
  • cond
  • 92.13 %
  • toggle
  • 94.30 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 20.640s 565.554us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.490s 78.478us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.060s 289.247us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 312.890s 10301.298us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 154.370s 3329.134us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 9.150s 145.657us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.060s 289.247us 1 1 100.00
alert_handler_csr_aliasing 154.370s 3329.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 79.450s 13801.532us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 17.560s 1636.553us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 399.060s 9684.767us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 31.240s 912.101us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 20.640s 565.554us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 23.930s 411.792us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 23.040s 2385.937us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 172.550s 40657.471us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1197.310s 60952.347us 1 1 100.00
alert_handler_lpg_stub_clk 931.010s 96184.076us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 23.070s 440.375us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 30.450s 2049.545us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.130s 31.983us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.840s 10.405us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.910s 141.966us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.910s 141.966us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.490s 78.478us 1 1 100.00
alert_handler_csr_rw 5.060s 289.247us 1 1 100.00
alert_handler_csr_aliasing 154.370s 3329.134us 1 1 100.00
alert_handler_same_csr_outstanding 12.250s 340.230us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.490s 78.478us 1 1 100.00
alert_handler_csr_rw 5.060s 289.247us 1 1 100.00
alert_handler_csr_aliasing 154.370s 3329.134us 1 1 100.00
alert_handler_same_csr_outstanding 12.250s 340.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 59.810s 924.675us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 59.810s 924.675us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 59.810s 924.675us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 59.810s 924.675us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 440.700s 19310.567us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_tl_intg_err 20.700s 447.198us 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 20.700s 447.198us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 59.810s 924.675us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 20.640s 565.554us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 20.640s 565.554us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 20.640s 565.554us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 20.640s 565.554us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 31.240s 912.101us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1197.310s 60952.347us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 31.240s 912.101us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 399.060s 9684.767us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 399.060s 9684.767us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.820s 991.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 222.240s 5364.053us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 69178209227055504101839872282547697241902577496990544165022314197486064769487 108
UVM_ERROR @ 40657470999 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 40657470999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---