Simulation Results: chip

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.91 %
  • code
  • 84.67 %
  • assert
  • 97.50 %
  • func
  • 51.56 %
  • line
  • 93.99 %
  • branch
  • 92.31 %
  • cond
  • 88.60 %
  • toggle
  • 91.31 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
82.01%
V2S
100.00%
V3
65.38%
unmapped
62.50%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 125.030s 3056.959us 1 1 100.00
chip_sw_example_rom 56.300s 2004.567us 1 1 100.00
chip_sw_example_manufacturer 152.760s 3209.060us 1 1 100.00
chip_sw_example_concurrency 137.070s 2609.449us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 274.470s 7891.913us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 328.980s 5094.406us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 4199.470s 58819.809us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3183.040s 28897.497us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 287.470s 6049.521us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3183.040s 28897.497us 1 1 100.00
chip_csr_rw 328.980s 5094.406us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.920s 45.938us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 299.290s 4416.791us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 299.290s 4416.791us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 299.290s 4416.791us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 375.580s 4499.246us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 375.580s 4499.246us 1 1 100.00
chip_sw_uart_tx_rx_idx1 385.250s 4492.032us 1 1 100.00
chip_sw_uart_tx_rx_idx2 375.010s 4176.289us 1 1 100.00
chip_sw_uart_tx_rx_idx3 389.240s 4658.727us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 968.040s 8658.511us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 321.370s 3993.659us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 607.270s 8270.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 198.990s 5299.424us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 198.990s 5299.424us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 177.240s 3345.173us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 151.980s 2648.514us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 153.200s 3852.721us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 91.990s 2585.892us 1 1 100.00
chip_tap_straps_testunlock0 482.530s 8158.380us 1 1 100.00
chip_tap_straps_rma 426.230s 7504.224us 1 1 100.00
chip_tap_straps_prod 202.710s 4820.210us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 141.420s 2634.720us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 703.330s 8874.048us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 417.900s 5951.406us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 417.900s 5951.406us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 552.320s 6559.353us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1512.050s 14621.785us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 335.080s 4327.686us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 586.240s 5799.116us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3590.730s 18496.276us 1 1 100.00
chip_sw_aes_enc_jitter_en 145.860s 2816.934us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 816.700s 7642.236us 1 1 100.00
chip_sw_hmac_enc_jitter_en 158.300s 2703.981us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1667.090s 13101.804us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 196.840s 3240.700us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 357.120s 4452.272us 1 1 100.00
chip_sw_clkmgr_jitter 153.510s 3311.619us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 153.890s 3071.445us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 425.570s 5020.992us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 264.390s 5212.319us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 136.730s 2893.986us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 264.390s 5212.319us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 174.030s 2572.516us 1 1 100.00
chip_sw_aes_smoketest 189.810s 2931.042us 1 1 100.00
chip_sw_aon_timer_smoketest 188.150s 3349.361us 1 1 100.00
chip_sw_clkmgr_smoketest 139.150s 3470.167us 1 1 100.00
chip_sw_csrng_smoketest 146.330s 2657.570us 1 1 100.00
chip_sw_entropy_src_smoketest 630.440s 6172.481us 1 1 100.00
chip_sw_gpio_smoketest 154.970s 3257.592us 1 1 100.00
chip_sw_hmac_smoketest 222.610s 3827.520us 1 1 100.00
chip_sw_kmac_smoketest 166.840s 3219.820us 1 1 100.00
chip_sw_otbn_smoketest 1028.960s 9153.345us 1 1 100.00
chip_sw_pwrmgr_smoketest 305.800s 5326.128us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 269.850s 5348.798us 1 1 100.00
chip_sw_rv_plic_smoketest 161.750s 2943.192us 1 1 100.00
chip_sw_rv_timer_smoketest 163.410s 3261.677us 1 1 100.00
chip_sw_rstmgr_smoketest 162.830s 2901.420us 1 1 100.00
chip_sw_sram_ctrl_smoketest 165.070s 3535.101us 1 1 100.00
chip_sw_uart_smoketest 175.790s 3210.207us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 172.880s 3278.874us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 354.870s 5854.586us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8080.400s 63932.504us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2434.630s 15214.739us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 178.830s 5232.030us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 155.430s 3234.502us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 183.960s 3244.640us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7120.500s 54469.110us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7325.880s 57909.965us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
chip_tl_errors 124.700s 3784.294us 1 1 100.00
tl_d_illegal_access 1 1 100.00
chip_tl_errors 124.700s 3784.294us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3183.040s 28897.497us 1 1 100.00
chip_same_csr_outstanding 2258.490s 31076.701us 1 1 100.00
chip_csr_hw_reset 274.470s 7891.913us 1 1 100.00
chip_csr_rw 328.980s 5094.406us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3183.040s 28897.497us 1 1 100.00
chip_same_csr_outstanding 2258.490s 31076.701us 1 1 100.00
chip_csr_hw_reset 274.470s 7891.913us 1 1 100.00
chip_csr_rw 328.980s 5094.406us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 33.380s 1312.977us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.840s 49.746us 1 1 100.00
xbar_smoke_large_delays 58.580s 8003.694us 1 1 100.00
xbar_smoke_slow_rsp 57.170s 6352.403us 1 1 100.00
xbar_random_zero_delays 20.600s 387.267us 1 1 100.00
xbar_random_large_delays 33.540s 5241.880us 1 1 100.00
xbar_random_slow_rsp 252.080s 28434.505us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 9.240s 79.707us 1 1 100.00
xbar_error_and_unmapped_addr 18.440s 664.620us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 11.400s 188.198us 1 1 100.00
xbar_error_and_unmapped_addr 18.440s 664.620us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 90.480s 3181.842us 1 1 100.00
xbar_access_same_device_slow_rsp 509.670s 55637.277us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 6.400s 185.503us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 400.760s 16342.933us 1 1 100.00
xbar_stress_all_with_error 20.220s 728.018us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 61.600s 1692.265us 1 1 100.00
xbar_stress_all_with_reset_error 181.260s 7164.353us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2434.630s 15214.739us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2170.990s 25660.070us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2547.080s 15258.070us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2093.000s 11814.060us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2647.400s 15812.522us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2538.990s 15576.882us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2599.480s 16606.516us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2559.340s 15344.682us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 19.530s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 16.950s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 19.710s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 16.440s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 16.660s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 17.210s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 17.910s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 18.560s 10.100us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 17.980s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17.720s 10.300us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.300s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.760s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.480s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 16.570s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.660s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.370s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.580s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.800s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.990s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.680s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 17.110s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 15.790s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.310s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 29.560s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 16.850s 10.360us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1972.130s 11584.871us 1 1 100.00
rom_e2e_asm_init_dev 2482.710s 16439.658us 1 1 100.00
rom_e2e_asm_init_prod 2443.300s 15568.695us 1 1 100.00
rom_e2e_asm_init_prod_end 2422.790s 16507.284us 1 1 100.00
rom_e2e_asm_init_rma 2349.750s 15807.926us 1 1 100.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 4255.620s 31781.933us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 2400.110s 17071.374us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2449.920s 16493.545us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2439.920s 15941.161us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2946.120s 35285.517us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2946.120s 35285.517us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 182.900s 3094.364us 1 1 100.00
chip_sw_aes_enc_jitter_en 145.860s 2816.934us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 167.080s 3139.206us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 146.090s 2984.712us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1796.490s 12684.446us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 178.830s 3620.216us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 337.110s 4405.248us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 415.990s 6171.305us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 539.950s 5233.713us 1 1 100.00
chip_plic_all_irqs_10 247.300s 3562.847us 1 1 100.00
chip_plic_all_irqs_20 381.570s 4177.277us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 247.960s 3569.079us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 946.480s 11418.178us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 196.870s 3772.564us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 166.890s 2701.553us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 607.840s 5657.698us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1088.470s 9067.473us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 729.960s 7938.371us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 6966.380s 254726.778us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 271.520s 4160.895us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 305.800s 5326.128us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 271.520s 4160.895us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 388.100s 7973.146us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 388.100s 7973.146us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 297.200s 6902.865us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 318.610s 5997.415us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 607.150s 6049.102us 1 1 100.00
chip_sw_aes_idle 146.090s 2984.712us 1 1 100.00
chip_sw_hmac_enc_idle 162.820s 3794.765us 1 1 100.00
chip_sw_kmac_idle 169.390s 3047.062us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 255.600s 4473.724us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 224.160s 4501.555us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 307.070s 5394.115us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 288.470s 4298.534us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 600.380s 9199.181us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 403.250s 4771.643us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 331.030s 4801.938us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 385.270s 4365.533us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 396.340s 4400.644us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 359.160s 4220.539us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 359.050s 4613.221us 1 1 100.00
chip_sw_ast_clk_outputs 552.320s 6559.353us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 358.390s 7473.222us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 385.270s 4365.533us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 396.340s 4400.644us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 335.080s 4327.686us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 586.240s 5799.116us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3590.730s 18496.276us 1 1 100.00
chip_sw_aes_enc_jitter_en 145.860s 2816.934us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 816.700s 7642.236us 1 1 100.00
chip_sw_hmac_enc_jitter_en 158.300s 2703.981us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1667.090s 13101.804us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 196.840s 3240.700us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 357.120s 4452.272us 1 1 100.00
chip_sw_clkmgr_jitter 153.510s 3311.619us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 123.560s 2824.293us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 393.510s 4467.085us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 632.070s 7540.077us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3109.960s 24799.474us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 138.280s 2873.302us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 162.470s 3528.960us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1158.910s 12398.070us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 199.560s 3251.091us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 357.260s 5105.680us 1 1 100.00
chip_sw_flash_init_reduced_freq 1101.770s 25260.785us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 19036.890s 239298.825us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 552.320s 6559.353us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 394.180s 4873.517us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 297.220s 3719.267us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 415.990s 6171.305us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 607.840s 5657.698us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1005.930s 7448.625us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 135.620s 2721.927us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 551.040s 7328.752us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 174.830s 2702.622us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2852.490s 19339.464us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 146.250s 3239.291us 1 1 100.00
chip_sw_edn_entropy_reqs 623.170s 5880.854us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 146.250s 3239.291us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1005.930s 7448.625us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 144.370s 3162.341us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1354.600s 25462.653us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 619.900s 5570.618us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 586.240s 5799.116us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 392.010s 3804.466us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 335.080s 4327.686us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3523.530s 42545.433us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1354.600s 25462.653us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 210.120s 3564.851us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1139.770s 10261.282us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.890s 2714.090us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3523.530s 42545.433us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.890s 2714.090us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.890s 2714.090us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.890s 2714.090us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.890s 2714.090us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 415.990s 6171.305us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 124.420s 5626.147us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 524.040s 4567.801us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 414.700s 6071.057us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 414.700s 6071.057us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 173.490s 3380.084us 1 1 100.00
chip_sw_hmac_enc_jitter_en 158.300s 2703.981us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 162.820s 3794.765us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1091.870s 8344.751us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 677.600s 6533.011us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 431.670s 5169.143us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 405.390s 5625.110us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 395.770s 4834.538us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 287.300s 4011.805us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1139.770s 10261.282us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1667.090s 13101.804us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1196.730s 10442.261us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1796.490s 12684.446us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 1875.640s 10645.057us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 134.360s 3269.081us 1 1 100.00
chip_sw_kmac_mode_kmac 208.220s 3513.725us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 196.840s 3240.700us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1139.770s 10261.282us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 400.490s 7348.832us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 161.740s 2662.764us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 852.130s 7011.835us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 169.390s 3047.062us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 337.110s 4405.248us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 91.990s 2585.892us 1 1 100.00
chip_tap_straps_rma 426.230s 7504.224us 1 1 100.00
chip_tap_straps_prod 202.710s 4820.210us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 147.380s 3150.958us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 400.490s 7348.832us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 400.490s 7348.832us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 400.490s 7348.832us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1698.700s 13593.725us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_prim_tl_access 124.420s 5626.147us 1 1 100.00
chip_rv_dm_lc_disabled 133.230s 5708.361us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 196.890s 2714.090us 0 1 0.00
chip_sw_flash_rma_unlocked 3523.530s 42545.433us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 222.600s 3272.153us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 538.850s 6180.189us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 489.550s 7859.585us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 532.470s 7373.981us 0 1 0.00
chip_sw_lc_ctrl_transition 400.490s 7348.832us 1 1 100.00
chip_sw_keymgr_key_derivation 1139.770s 10261.282us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 345.930s 8645.719us 1 1 100.00
chip_sw_sram_ctrl_execution_main 616.070s 8633.968us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 358.390s 7473.222us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 403.250s 4771.643us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 331.030s 4801.938us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 385.270s 4365.533us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 396.340s 4400.644us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 359.160s 4220.539us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 359.050s 4613.221us 1 1 100.00
chip_tap_straps_dev 91.990s 2585.892us 1 1 100.00
chip_tap_straps_rma 426.230s 7504.224us 1 1 100.00
chip_tap_straps_prod 202.710s 4820.210us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 186.760s 3619.866us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 99.550s 3650.244us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 98.790s 4014.134us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 75.700s 3341.229us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 133.230s 5708.361us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2075.880s 37002.075us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 678.270s 10604.891us 0 1 0.00
chip_sw_lc_walkthrough_prod 646.300s 9909.888us 0 1 0.00
chip_sw_lc_walkthrough_prodend 752.120s 10690.472us 1 1 100.00
chip_sw_lc_walkthrough_rma 378.990s 7966.280us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2075.880s 37002.075us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 57.490s 2392.595us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 60.520s 3120.536us 1 1 100.00
rom_volatile_raw_unlock 68.860s 1955.446us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3517.460s 16737.452us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3590.730s 18496.276us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 607.150s 6049.102us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 607.150s 6049.102us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 607.150s 6049.102us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 306.340s 3816.897us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 400.490s 7348.832us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1354.600s 25462.653us 1 1 100.00
chip_sw_otbn_mem_scramble 306.340s 3816.897us 1 1 100.00
chip_sw_keymgr_key_derivation 1139.770s 10261.282us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 343.480s 4415.268us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 170.080s 3491.478us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1354.600s 25462.653us 1 1 100.00
chip_sw_otbn_mem_scramble 306.340s 3816.897us 1 1 100.00
chip_sw_keymgr_key_derivation 1139.770s 10261.282us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 343.480s 4415.268us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 170.080s 3491.478us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 400.490s 7348.832us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 399.270s 5748.677us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 147.380s 3150.958us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 124.420s 5626.147us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 222.600s 3272.153us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 538.850s 6180.189us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 489.550s 7859.585us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 532.470s 7373.981us 0 1 0.00
chip_sw_lc_ctrl_transition 400.490s 7348.832us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 124.420s 5626.147us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 832.920s 8061.098us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 314.810s 8558.860us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 945.420s 23436.151us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 261.100s 7410.685us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 359.730s 7894.300us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 439.550s 8053.655us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 810.970s 21559.763us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 518.910s 10444.404us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 388.100s 7973.146us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 723.430s 12094.054us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 330.170s 5315.135us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 314.810s 8558.860us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 232.190s 4589.375us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1730.610s 31161.601us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 276.040s 6101.995us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 310.830s 4883.374us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 616.030s 13507.908us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 570.300s 6278.342us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1081.620s 11672.567us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1456.810s 31873.850us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 166.470s 3059.592us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 415.990s 6171.305us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 345.930s 8645.719us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 345.930s 8645.719us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1081.620s 11672.567us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 616.030s 13507.908us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 330.170s 5315.135us 1 1 100.00
chip_sw_pwrmgr_smoketest 305.800s 5326.128us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 321.180s 4621.274us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 242.880s 3745.503us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 309.660s 4663.019us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 946.480s 11418.178us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 152.270s 2591.588us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 415.990s 6171.305us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1088.470s 9067.473us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 487.970s 4373.320us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 531.670s 5338.559us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 168.500s 3117.738us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 170.080s 3491.478us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 242.880s 3745.503us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 242.880s 3745.503us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 479.760s 9238.239us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1001.890s 14348.664us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 321.180s 4621.274us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 141.770s 2884.429us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 313.010s 5876.858us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 426.230s 7504.224us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 133.230s 5708.361us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 539.950s 5233.713us 1 1 100.00
chip_plic_all_irqs_10 247.300s 3562.847us 1 1 100.00
chip_plic_all_irqs_20 381.570s 4177.277us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 196.210s 3763.873us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 162.930s 2624.096us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2434.630s 15214.739us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 465.510s 7740.283us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 201.280s 3476.890us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 238.770s 3599.523us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 144.130s 2592.159us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 343.480s 4415.268us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 357.120s 4452.272us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 375.120s 6278.733us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 441.570s 8012.933us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 616.070s 8633.968us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 415.990s 6171.305us 1 1 100.00
chip_sw_data_integrity_escalation 417.900s 5951.406us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 570.300s 6278.342us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1050.680s 23121.921us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 178.610s 2941.874us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 201.870s 3448.893us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 295.360s 4632.225us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1050.680s 23121.921us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1050.680s 23121.921us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2447.460s 20491.836us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2447.460s 20491.836us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 254.140s 4970.510us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2946.120s 35285.517us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 164.210s 3549.156us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 174.940s 3000.676us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 265.870s 3908.784us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 306.200s 3731.597us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1032.530s 7836.492us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4797.180s 31404.535us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1786.500s 12202.763us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 129.750s 2510.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 222.330s 3065.641us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 127.550s 2802.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 8788.420s 71815.624us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1038.790s 6550.565us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 165.340s 2888.011us 0 1 0.00
rom_e2e_jtag_debug_dev 482.010s 6281.607us 0 1 0.00
rom_e2e_jtag_debug_rma 169.640s 4094.086us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 65.770s 1873.927us 0 1 0.00
rom_e2e_jtag_inject_dev 68.530s 3073.987us 0 1 0.00
rom_e2e_jtag_inject_rma 74.280s 2703.525us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 8.764s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 275.070s 4059.585us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 327.270s 3159.380us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 667.170s 5215.962us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 927.590s 6919.389us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 224.450s 2365.213us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 567.630s 4957.245us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 55.660s 2110.672us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 219.680s 3903.826us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 237.510s 5320.848us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 299.630s 4707.582us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1081.620s 11672.567us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 165.340s 2888.011us 0 1 0.00
rom_e2e_jtag_debug_dev 482.010s 6281.607us 0 1 0.00
rom_e2e_jtag_debug_rma 169.640s 4094.086us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 457.290s 6273.221us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 415.990s 6171.305us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5426.700s 38025.761us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5426.700s 38025.761us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 132.290s 3461.594us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 375.580s 4499.246us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3055.840s 18827.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 5 8 62.50
chip_sival_flash_info_access 195.100s 3755.919us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 490.800s 6881.989us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 7.080s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 162.770s 3142.465us 1 1 100.00
chip_sw_otp_ctrl_descrambling 219.300s 3260.956us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 161.010s 3094.933us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 11.395s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 147.240s 2761.323us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 83790432014991020402217891378751887633791061190362238404384499534135616444453 237
UVM_ERROR @ 5708.360779 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10590 read out mismatch
UVM_INFO @ 5708.360779 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_csr_mem_rw_with_rand_reset 35720031239653219731941005339531536971739725020028844583056338517426119761359 242
UVM_ERROR @ 6049.521475 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@217687) { a_addr: 'h107e8 a_data: 'h865a3546 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h18da0 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 6049.521475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 17640264886559387271062763847635780007395302499075333364441705495868255706553 333
UVM_ERROR @ 3745.502768 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@106591) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 3745.502768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 114042145369200031834594649913973459711797952006004227078286699828650029270223 451
UVM_ERROR @ 3345.173000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 3345.173000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 73618719261831317776008845771924471531779556603228589470487487611566576927456 320
UVM_ERROR @ 3476.890388 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3476.890388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 112305801835379677655965688339892563902674708894730555992518182601456182423408 309
UVM_ERROR @ 2714.089680 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 2714.089680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 82980923852253783403593279924891564043063656293957799408543512851886577960105 342
UVM_ERROR @ 7373.980960 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7373.980960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 14713737971746736498073569103094794790612943036506413402253573967972544549503 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3903.826074 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3903.826074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 64237685850967310783056861602839558126307773453396278337356997333845528651136 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2721.927300 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2721.927300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 14267744006585899812998385506401477171279140293990757030150496685189238753748 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 85066072486798529127727815259783307485974783508544301945901519780044586738552 369
UVM_ERROR @ 10604.890606 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 10604.890606 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 3319560820894178748702242591911370011312486504679056838899977278037798336049 369
UVM_ERROR @ 9909.887652 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 9909.887652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 20840860210495691583940313332688627850184647737691298128159404668977114585567 341
UVM_ERROR @ 7966.279625 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 7966.279625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 20010710090425097564916639300594696450346212016790091203162645311532276302092 344
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 13507.908000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13507.908000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 85203615318727432708067618804197154825677908070613126980460668140838737063685 327
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 10444.404000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10444.404000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 129018624891252635361473435876783677944806864054011895289095189409816515606 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7894.300000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7894.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 109807297208179728611656730922483762175689022108803230220287256574291049892836 319
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 7973.146000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7973.146000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 39833656998017869999247750283588649726364896292763519845770229060393279341991 332
UVM_ERROR @ 35285.517059 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 35285.517059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:412)] CHECK-fail: Expect alert *!
chip_sw_alert_test 42332783334634758751401965746780807105422139670031432615905295947440741868899 307
UVM_ERROR @ 3620.216086 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:412)] CHECK-fail: Expect alert 36!
UVM_INFO @ 3620.216086 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 23163227456526339140371328018933928265758982232260164883605843349691499914993 308
UVM_ERROR @ 2701.552940 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2701.552940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 61669177895700872195313747242510267762075980450945337373953615501966737940288 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 115468883770593264501776268300328013911711895888495861724276866027017081465782 343
UVM_ERROR @ 4059.585130 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 4059.585130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 73944963287249714676836328239975620124940920006459224197528538952895584585965 311
UVM_ERROR @ 3094.932576 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 3094.932576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 65879763657115081292616172552843975867454813831999551209253784604354790777887 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 17218859343753567585786450636518376137663587044658026602062081111465652570482 None
---- STDERR ----
Another command (pid=2538959) is running. Waiting for it to complete on the server (server_pid=930023)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 46174013775040275068486689171127937054340270752347282840478725420963030544811 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 2393340428304930814712359183213936673638495425478477412847390910792377922587 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 46800020290724083237445782001778798281489564655106299860861506063613680852500 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 11642077450576509820394165173951064549399476834499052050139223931740786864470 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 46014721723468253889454519135608458441688607106955478124922811765383190887265 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 14002615126523922291693154424778956693792898499300206305086781347447904628800 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 74070025579579793973008747771817499350794560272278041270116142560572549266072 307
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 92110643488579317096616485169223642285084929579647797459527094728543167152533 312
UVM_ERROR @ 3234.502000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3234.502000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 115529948439860544036975217754158427227153915798563876957058675959126059349781 318
UVM_ERROR @ 3244.639500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3244.639500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 95181926043957604164114355239641062538096738924092890626649321466596047269640 327
UVM_ERROR @ 14621.784769 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 14621.784769 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 68259952543099954011021986830889534621962450022080278667506265921037504180231 351
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 70684390807060870473500760273459667949828810493880698331427090491511409387520 350
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 54328534285490157724847275925968723740093518604533504983952186738089543637797 351
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 35201430814472108600847266909325379197056633830806844348092161005635307776750 350
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 25352124299437623975782142107999476164085744317138383530569508707280798424449 351
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 1884677265647970390281907403835858834373055437170173971032272138368821204608 347
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 53269446853779513537600924653737406859014267012928037727882133804934945385708 346
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 59460909351721661403400079213207983350437954004741885318893031922618915378379 349
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 52173819448017196846942334582719639729176028461343154636394139267021424101981 348
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 94498750889887974648710604383539783886120193302198162246657969698222076414594 348
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 26286674219707818315992541980146296910679167472943738359805937672077945282317 356
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 77152828374525572397799429802651030457758611696406270386052490308059655292285 357
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 87143154438417567751879842184515690417393686765030899857578507665076324910043 358
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 50013663225266245791495163915595294135093272979386311419807692981621728343442 323
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 115762930408135875268719211471454798229349469632259737838984055111481233719375 324
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 65097614996263096629615259792836348677375141700956364924338312628121246712879 323
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 9669796874327567731530746470949493643206463092159587274118853085720047036449 358
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 20297919169793815005901471746684624179217209262725828168039827482368051904405 324
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 96306884436227048632203617343934529150746221704769445202452082045408220606534 357
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 35412624785097624922346116146679647274345821067621357892267827138378674128104 322
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 64768526200889481684603602843108820420881044403997325500330936737306756874274 322
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 71751797974237979853480335160828409143239557588100480175712581102982834087987 323
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 49964283165133515797096754405362300575180350330659633499864724417327170757771 323
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 10954288596788407048035228998702254176279082254291700869331423033150805964925 322
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 28385327012884913768601113610367692008207010961808719152923542319825695776372 323
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 96904815583013016201380871396433094093301613214036573440739126058438771916707 319
UVM_ERROR @ 17071.374150 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 17071.374150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 111613149617726215925978398480240455414162808681221838657967563177165407183264 319
UVM_ERROR @ 16493.545208 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16493.545208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 96436424051791111871604015217848916597632299279754717144396599392738715028505 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 5854.585995 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5854.585995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---