Simulation Results: clkmgr

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.43 %
  • code
  • 98.42 %
  • assert
  • 95.76 %
  • func
  • 86.11 %
  • line
  • 99.11 %
  • branch
  • 98.84 %
  • cond
  • 94.94 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.900s 67.590us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.900s 84.736us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.010s 17.296us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.490s 138.685us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.810s 302.345us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.100s 30.167us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.010s 17.296us 1 1 100.00
clkmgr_csr_aliasing 1.810s 302.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.700s 24.814us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.120s 86.022us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.810s 21.812us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.650s 16.910us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.900s 67.590us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 5.700s 1167.073us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.620s 742.773us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 5.700s 1167.073us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 22.750s 8188.504us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.890s 19.776us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.610s 177.937us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.610s 177.937us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.900s 84.736us 1 1 100.00
clkmgr_csr_rw 1.010s 17.296us 1 1 100.00
clkmgr_csr_aliasing 1.810s 302.345us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 37.721us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.900s 84.736us 1 1 100.00
clkmgr_csr_rw 1.010s 17.296us 1 1 100.00
clkmgr_csr_aliasing 1.810s 302.345us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 37.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.980s 5.156us 0 1 0.00
clkmgr_tl_intg_err 2.210s 158.641us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 107.775us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 107.775us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 107.775us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 107.775us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.450s 57.523us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.210s 158.641us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 5.700s 1167.073us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.620s 742.773us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 107.775us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.830s 27.018us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.780s 57.506us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.780s 16.819us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.900s 71.853us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.790s 15.918us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.010s 17.296us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.980s 5.156us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.010s 17.296us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.010s 17.296us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.980s 5.156us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 5.320s 1247.789us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 14.590s 1342.851us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 34047292861712185448187241856173486900094063428244626725330465213607807180694 81
UVM_ERROR @ 5156332 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 5156332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---