Simulation Results: csrng

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.07 %
  • code
  • 91.95 %
  • assert
  • 93.01 %
  • func
  • 64.26 %
  • block
  • 96.58 %
  • line
  • 97.30 %
  • branch
  • 91.41 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 28.905us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 75.666us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 41.708us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 12.000s 908.447us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 62.353us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 42.358us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 41.708us 1 1 100.00
csrng_csr_aliasing 2.000s 62.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
alerts 1 1 100.00
csrng_alert 3.000s 67.009us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 382.111us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 382.111us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 5.000s 116.518us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 48.994us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 24.391us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 11.000s 725.159us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 11.000s 725.159us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 75.666us 1 1 100.00
csrng_csr_rw 2.000s 41.708us 1 1 100.00
csrng_csr_aliasing 2.000s 62.353us 1 1 100.00
csrng_same_csr_outstanding 3.000s 104.370us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 75.666us 1 1 100.00
csrng_csr_rw 2.000s 41.708us 1 1 100.00
csrng_csr_aliasing 2.000s 62.353us 1 1 100.00
csrng_same_csr_outstanding 3.000s 104.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 43.868us 1 1 100.00
csrng_tl_intg_err 5.000s 125.119us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 14.954us 1 1 100.00
csrng_csr_rw 2.000s 41.708us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 3.000s 67.009us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 5.000s 116.518us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
csrng_sec_cm 3.000s 43.868us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
csrng_sec_cm 3.000s 43.868us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
csrng_sec_cm 3.000s 43.868us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
csrng_sec_cm 3.000s 43.868us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
csrng_sec_cm 3.000s 43.868us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 3.000s 67.009us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 5.000s 116.518us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 3.000s 67.009us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 125.119us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
csrng_sec_cm 3.000s 43.868us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
csrng_sec_cm 3.000s 43.868us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 9.000s 698.095us 1 1 100.00
csrng_err 2.000s 31.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*])
csrng_cmds 5657310960742657113154802566976950295176685921857998705475388383512478677858 149
UVM_FATAL @ 382110761 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3])
UVM_INFO @ 382110761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
csrng_stress_all_with_rand_reset 16204209237923895134667209562619772019138694639202768302793974555556603115880 None
Job timed out after 180 minutes