Simulation Results: edn/edn0

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.07 %
  • code
  • 79.48 %
  • assert
  • 94.36 %
  • func
  • 78.37 %
  • line
  • 96.79 %
  • branch
  • 88.42 %
  • cond
  • 83.40 %
  • toggle
  • 77.20 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.990s 17.713us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.890s 52.872us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 45.918us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.890s 878.292us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.950s 29.076us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.840s 52.424us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 45.918us 1 1 100.00
edn_csr_aliasing 0.950s 29.076us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.230s 38.465us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.230s 38.465us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.230s 38.465us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.790s 57.030us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.900s 86.073us 1 1 100.00
errs 1 1 100.00
edn_err 0.940s 20.721us 1 1 100.00
disable 2 2 100.00
edn_disable 0.800s 13.085us 1 1 100.00
edn_disable_auto_req_mode 0.870s 41.070us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.140s 190.801us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.750s 36.751us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.740s 48.088us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.750s 57.500us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.750s 57.500us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.890s 52.872us 1 1 100.00
edn_csr_rw 0.770s 45.918us 1 1 100.00
edn_csr_aliasing 0.950s 29.076us 1 1 100.00
edn_same_csr_outstanding 1.020s 29.402us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.890s 52.872us 1 1 100.00
edn_csr_rw 0.770s 45.918us 1 1 100.00
edn_csr_aliasing 0.950s 29.076us 1 1 100.00
edn_same_csr_outstanding 1.020s 29.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.130s 99.248us 1 1 100.00
edn_sec_cm 7.960s 740.289us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 23.217us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.900s 86.073us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.960s 740.289us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.960s 740.289us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.960s 740.289us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.960s 740.289us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.900s 86.073us 1 1 100.00
edn_sec_cm 7.960s 740.289us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.900s 86.073us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.130s 99.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 44.610s 8158.895us 1 1 100.00