Simulation Results: edn/edn1

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.40 %
  • code
  • 82.45 %
  • assert
  • 97.14 %
  • func
  • 79.62 %
  • line
  • 98.33 %
  • branch
  • 93.72 %
  • cond
  • 88.54 %
  • toggle
  • 87.36 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.770s 25.679us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.910s 19.870us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 49.259us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.160s 122.378us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.920s 27.316us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.130s 179.356us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 49.259us 1 1 100.00
edn_csr_aliasing 0.920s 27.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.660s 291.802us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.660s 291.802us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.660s 291.802us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.820s 50.500us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 93.797us 1 1 100.00
errs 1 1 100.00
edn_err 1.070s 28.118us 1 1 100.00
disable 2 2 100.00
edn_disable 0.710s 21.681us 1 1 100.00
edn_disable_auto_req_mode 0.900s 46.371us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.070s 270.764us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.900s 51.930us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.800s 21.636us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.660s 125.522us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.660s 125.522us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.910s 19.870us 1 1 100.00
edn_csr_rw 0.740s 49.259us 1 1 100.00
edn_csr_aliasing 0.920s 27.316us 1 1 100.00
edn_same_csr_outstanding 1.120s 45.583us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.910s 19.870us 1 1 100.00
edn_csr_rw 0.740s 49.259us 1 1 100.00
edn_csr_aliasing 0.920s 27.316us 1 1 100.00
edn_same_csr_outstanding 1.120s 45.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.740s 375.546us 1 1 100.00
edn_sec_cm 2.260s 466.990us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.700s 87.484us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 93.797us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.260s 466.990us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.260s 466.990us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.260s 466.990us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.260s 466.990us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 93.797us 1 1 100.00
edn_sec_cm 2.260s 466.990us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 93.797us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.740s 375.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 48.450s 1873.124us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 62625840860153918127315630505336555020439441490931364660398815725150366574743 220
UVM_ERROR @ 1873123532 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1873123532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---