Simulation Results: flash_ctrl

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 94.13 %
  • assert
  • 96.50 %
  • func
  • 95.79 %
  • line
  • 95.99 %
  • branch
  • 97.16 %
  • cond
  • 93.76 %
  • toggle
  • 98.01 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 51.030s 28.543us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.380s 18.227us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 19.680s 89.920us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.480s 68.662us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 46.780s 2482.776us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 21.040s 1425.971us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.470s 167.147us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.480s 68.662us 1 1 100.00
flash_ctrl_csr_aliasing 21.040s 1425.971us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.370s 87.896us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.290s 16.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.510s 21.898us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 33.830s 236.856us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1253.410s 181339.786us 1 1 100.00
flash_ctrl_hw_rma_reset 549.710s 60138.514us 1 1 100.00
flash_ctrl_lcmgr_intg 6.860s 23.629us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1407.050s 387754.035us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 261.560s 3358.103us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.250s 39.157us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 3083.310s 407925.839us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 36.040s 78.037us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.790s 115.734us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.680s 66.639us 1 1 100.00
flash_ctrl_re_evict 16.290s 82.819us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 120.240s 92.152us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 120.240s 92.152us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 447.230s 17172.490us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 9.700s 459.794us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 214.000s 252.142us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 365.740s 21806.709us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 267.500s 1091.096us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 958.560s 1081.593us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.530s 22.659us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 103.530s 985.538us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.560s 55.487us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.200s 34.798us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 261.890s 245.099us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 59.410s 2753.448us 1 1 100.00
flash_ctrl_otp_reset 51.340s 695.574us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1253.410s 181339.786us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 71.630s 1066.786us 1 1 100.00
flash_ctrl_intr_wr 46.630s 10036.317us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 78.940s 11451.179us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 144.490s 26366.650us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 52.910s 2724.860us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.800s 1679.271us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.800s 26.427us 1 1 100.00
flash_ctrl_ro_derr 76.890s 830.792us 1 1 100.00
flash_ctrl_rw_derr 140.600s 6366.268us 1 1 100.00
flash_ctrl_derr_detect 112.960s 929.807us 1 1 100.00
flash_ctrl_integrity 499.520s 69417.909us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.720s 90.665us 1 1 100.00
flash_ctrl_ro_serr 88.820s 744.450us 1 1 100.00
flash_ctrl_rw_serr 134.270s 3455.838us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 42.040s 634.976us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 35.480s 2170.777us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 174.350s 7921.686us 1 1 100.00
flash_ctrl_write_word_sweep 9.910s 45.868us 1 1 100.00
flash_ctrl_read_word_sweep 6.230s 180.769us 1 1 100.00
flash_ctrl_ro 81.820s 746.801us 1 1 100.00
flash_ctrl_rw 349.310s 7620.042us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 25.340s 356.550us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 624.020s 157507.750us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 30.580s 10090.968us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.130s 127.543us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 9.250s 19.950us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.390s 135.135us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.390s 135.135us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 19.680s 89.920us 1 1 100.00
flash_ctrl_csr_rw 7.480s 68.662us 1 1 100.00
flash_ctrl_csr_aliasing 21.040s 1425.971us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.110s 65.368us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 19.680s 89.920us 1 1 100.00
flash_ctrl_csr_rw 7.480s 68.662us 1 1 100.00
flash_ctrl_csr_aliasing 21.040s 1425.971us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.110s 65.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 17.760s 29.431us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 17.760s 29.431us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 17.760s 29.431us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 17.760s 29.431us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 32.140s 266.366us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 351.190s 1462.226us 1 1 100.00
flash_ctrl_sec_cm 1530.130s 1399.314us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 351.190s 1462.226us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 351.190s 1462.226us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 13.260s 216.721us 1 1 100.00
flash_ctrl_wr_intg 6.710s 47.903us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 51.030s 28.543us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 51.340s 695.574us 1 1 100.00
flash_ctrl_disable 9.560s 55.487us 1 1 100.00
flash_ctrl_sec_info_access 40.790s 602.364us 1 1 100.00
flash_ctrl_connect 8.200s 34.798us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.830s 39.684us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.480s 68.662us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 17.760s 29.431us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.480s 68.662us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 17.760s 29.431us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.480s 68.662us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 17.760s 29.431us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.560s 55.487us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 13.260s 216.721us 1 1 100.00
flash_ctrl_access_after_disable 7.960s 19.695us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 11.530s 40.596us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.560s 55.487us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 9.700s 459.794us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 349.310s 7620.042us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 134.270s 3455.838us 1 1 100.00
flash_ctrl_rw_derr 140.600s 6366.268us 1 1 100.00
flash_ctrl_integrity 499.520s 69417.909us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1253.410s 181339.786us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.130s 1399.314us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.130s 1399.314us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.130s 1399.314us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1530.130s 1399.314us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.570s 847.860us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 10.270s 22.136us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 5.920s 65.878us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1530.130s 1399.314us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.130s 1399.314us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1530.130s 1399.314us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.330s 340.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 365.660s 2087.436us 1 1 100.00