| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.240s | 83.713us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 0.690s | 41.040us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 0.920s | 86.698us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 0.930s | 52.504us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.580s | 25.049us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.800s | 43.303us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 2.240s | 312.391us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 0.730s | 45.898us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 0.690s | 56.557us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 0.800s | 43.303us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.730s | 45.898us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 0.730s | 133.391us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 0.870s | 311.026us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.620s | 71.570us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 1.120s | 439.378us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 0.960s | 27.309us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 1.830s | 942.443us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 5.170s | 283.642us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 2.420s | 707.313us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 0.920s | 68.955us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 9.370s | 1155.735us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.600s | 29.783us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.640s | 14.365us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.500s | 33.615us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.500s | 33.615us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.800s | 43.303us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.740s | 171.563us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.730s | 45.898us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.580s | 25.049us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.800s | 43.303us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.740s | 171.563us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.730s | 45.898us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.580s | 25.049us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_sec_cm | 1.080s | 105.315us | 1 | 1 | 100.00 | |
| gpio_tl_intg_err | 1.360s | 410.947us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 1.360s | 410.947us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.640s | 31.431us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 4.450s | 377.995us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| gpio_stress_all | 43537658601218681329984559991906229788986503664933591210117081702640485735873 | 82 |
UVM_ERROR @ 1155734959 ps: (gpio_scoreboard.sv:216) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1883752229 [0x7047c725] vs 4086453225 [0xf39253e9])
UVM_INFO @ 1155734959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | ||||
| gpio_stress_all_with_rand_reset | 73276482981983573121462008345036776385222671275447966407690248661800839381673 | 221 |
UVM_FATAL @ 377994516 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -1
UVM_INFO @ 377994516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|