Simulation Results: hmac

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.63 %
  • code
  • 97.45 %
  • assert
  • 97.36 %
  • func
  • 44.07 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.68 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 12.370s 5618.663us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.670s 43.568us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.890s 78.414us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.500s 1901.061us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.160s 62.512us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 175.210s 25259.166us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.890s 78.414us 1 1 100.00
hmac_csr_aliasing 2.160s 62.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 53.810s 9082.649us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 39.160s 3867.797us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 180.780s 5450.830us 1 1 100.00
hmac_test_sha384_vectors 409.140s 59888.477us 1 1 100.00
hmac_test_sha512_vectors 19.270s 2730.917us 1 1 100.00
hmac_test_hmac256_vectors 7.420s 480.887us 1 1 100.00
hmac_test_hmac384_vectors 5.770s 693.040us 1 1 100.00
hmac_test_hmac512_vectors 7.440s 460.103us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 18.050s 7882.715us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 393.990s 2852.567us 1 1 100.00
error 1 1 100.00
hmac_error 30.230s 2831.449us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 55.050s 1554.932us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 12.370s 5618.663us 1 1 100.00
hmac_long_msg 53.810s 9082.649us 1 1 100.00
hmac_back_pressure 39.160s 3867.797us 1 1 100.00
hmac_datapath_stress 393.990s 2852.567us 1 1 100.00
hmac_burst_wr 18.050s 7882.715us 1 1 100.00
hmac_stress_all 2453.380s 229984.707us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 12.370s 5618.663us 1 1 100.00
hmac_long_msg 53.810s 9082.649us 1 1 100.00
hmac_back_pressure 39.160s 3867.797us 1 1 100.00
hmac_datapath_stress 393.990s 2852.567us 1 1 100.00
hmac_wipe_secret 55.050s 1554.932us 1 1 100.00
hmac_test_sha256_vectors 180.780s 5450.830us 1 1 100.00
hmac_test_sha384_vectors 409.140s 59888.477us 1 1 100.00
hmac_test_sha512_vectors 19.270s 2730.917us 1 1 100.00
hmac_test_hmac256_vectors 7.420s 480.887us 1 1 100.00
hmac_test_hmac384_vectors 5.770s 693.040us 1 1 100.00
hmac_test_hmac512_vectors 7.440s 460.103us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 12.370s 5618.663us 1 1 100.00
hmac_long_msg 53.810s 9082.649us 1 1 100.00
hmac_back_pressure 39.160s 3867.797us 1 1 100.00
hmac_datapath_stress 393.990s 2852.567us 1 1 100.00
hmac_burst_wr 18.050s 7882.715us 1 1 100.00
hmac_error 30.230s 2831.449us 1 1 100.00
hmac_wipe_secret 55.050s 1554.932us 1 1 100.00
hmac_test_sha256_vectors 180.780s 5450.830us 1 1 100.00
hmac_test_sha384_vectors 409.140s 59888.477us 1 1 100.00
hmac_test_sha512_vectors 19.270s 2730.917us 1 1 100.00
hmac_test_hmac256_vectors 7.420s 480.887us 1 1 100.00
hmac_test_hmac384_vectors 5.770s 693.040us 1 1 100.00
hmac_test_hmac512_vectors 7.440s 460.103us 1 1 100.00
hmac_stress_all 2453.380s 229984.707us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 2453.380s 229984.707us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.570s 66.563us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.740s 27.592us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.870s 374.666us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.870s 374.666us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.670s 43.568us 1 1 100.00
hmac_csr_rw 0.890s 78.414us 1 1 100.00
hmac_csr_aliasing 2.160s 62.512us 1 1 100.00
hmac_same_csr_outstanding 1.720s 272.576us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.670s 43.568us 1 1 100.00
hmac_csr_rw 0.890s 78.414us 1 1 100.00
hmac_csr_aliasing 2.160s 62.512us 1 1 100.00
hmac_same_csr_outstanding 1.720s 272.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 3.290s 523.134us 1 1 100.00
hmac_sec_cm 0.980s 104.844us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.290s 523.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 12.370s 5618.663us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.470s 260.369us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 83.980s 2179.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.780s 29.484us 1 1 100.00