Simulation Results: kmac/unmasked

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.86 %
  • code
  • 88.51 %
  • assert
  • 97.75 %
  • func
  • 89.32 %
  • line
  • 96.91 %
  • branch
  • 94.30 %
  • cond
  • 93.55 %
  • toggle
  • 99.96 %
  • FSM
  • 57.85 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 25.130s 1254.273us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.890s 153.766us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.960s 209.826us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 12.820s 1207.249us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.600s 507.700us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.530s 178.864us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.960s 209.826us 1 1 100.00
kmac_csr_aliasing 3.600s 507.700us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.670s 13.690us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.020s 64.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1168.240s 70810.933us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 284.670s 4674.252us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 33.790s 2642.937us 1 1 100.00
kmac_test_vectors_sha3_256 1413.230s 154098.086us 1 1 100.00
kmac_test_vectors_sha3_384 1206.790s 287941.956us 1 1 100.00
kmac_test_vectors_sha3_512 10.950s 4428.069us 1 1 100.00
kmac_test_vectors_shake_128 124.510s 44513.984us 1 1 100.00
kmac_test_vectors_shake_256 274.460s 29454.860us 1 1 100.00
kmac_test_vectors_kmac 2.490s 148.949us 1 1 100.00
kmac_test_vectors_kmac_xof 2.680s 74.649us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 220.750s 24052.638us 1 1 100.00
app 1 1 100.00
kmac_app 31.700s 13581.683us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 78.010s 24826.850us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 89.320s 3106.310us 1 1 100.00
error 1 1 100.00
kmac_error 5.860s 260.990us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 8.010s 14258.538us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 82.340s 10112.963us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 10.960s 757.363us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 21.750s 1219.759us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 16.810s 10451.384us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.580s 53.362us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 309.670s 10869.619us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.700s 37.194us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.840s 13.804us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.800s 77.741us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.800s 77.741us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.890s 153.766us 1 1 100.00
kmac_csr_rw 0.960s 209.826us 1 1 100.00
kmac_csr_aliasing 3.600s 507.700us 1 1 100.00
kmac_same_csr_outstanding 1.770s 74.432us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.890s 153.766us 1 1 100.00
kmac_csr_rw 0.960s 209.826us 1 1 100.00
kmac_csr_aliasing 3.600s 507.700us 1 1 100.00
kmac_same_csr_outstanding 1.770s 74.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.410s 160.130us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.410s 160.130us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.410s 160.130us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.410s 160.130us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.200s 418.305us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 2.110s 81.378us 1 1 100.00
kmac_sec_cm 51.000s 18441.240us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.110s 81.378us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.580s 53.362us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 25.130s 1254.273us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 220.750s 24052.638us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.410s 160.130us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 51.000s 18441.240us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 51.000s 18441.240us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 51.000s 18441.240us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 25.130s 1254.273us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.580s 53.362us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 51.000s 18441.240us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 87.700s 17896.313us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 25.130s 1254.273us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 20.950s 1162.961us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 114624635791920778216469932122934307881786205699095903483490332713091885021153 88
UVM_FATAL @ 10112963356 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9650c000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10112963356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---