Simulation Results: lc_ctrl/volatile_unlock_disabled

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.16 %
  • code
  • 83.82 %
  • assert
  • 94.13 %
  • func
  • 92.53 %
  • line
  • 97.08 %
  • branch
  • 93.67 %
  • cond
  • 78.95 %
  • toggle
  • 87.72 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.330s 79.404us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.280s 66.564us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.840s 15.456us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.030s 67.152us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.700s 407.568us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.040s 21.215us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.840s 15.456us 1 1 100.00
lc_ctrl_csr_aliasing 1.700s 407.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.450s 595.259us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.930s 300.022us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.050s 13.672us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.990s 110.431us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.270s 2518.584us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_ctrl_prog_failure 2.990s 110.431us 1 1 100.00
lc_ctrl_errors 7.270s 2518.584us 1 1 100.00
lc_ctrl_security_escalation 4.760s 292.396us 1 1 100.00
lc_ctrl_jtag_state_failure 30.260s 3112.557us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.800s 559.130us 1 1 100.00
lc_ctrl_jtag_errors 34.980s 7077.252us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 3.300s 2088.642us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.430s 78.129us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 16.350s 4099.190us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.400s 1134.137us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.120s 151.796us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.680s 467.660us 1 1 100.00
lc_ctrl_jtag_alert_test 0.940s 14.074us 1 1 100.00
lc_ctrl_jtag_smoke 11.140s 2492.252us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.280s 1367.237us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.800s 559.130us 1 1 100.00
lc_ctrl_jtag_errors 34.980s 7077.252us 1 1 100.00
lc_ctrl_jtag_access 1.910s 236.576us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.870s 4469.911us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.140s 744.151us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.040s 39.986us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 77.650s 13787.907us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.030s 30.173us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.240s 169.006us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.240s 169.006us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.280s 66.564us 1 1 100.00
lc_ctrl_csr_rw 0.840s 15.456us 1 1 100.00
lc_ctrl_csr_aliasing 1.700s 407.568us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 121.359us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.280s 66.564us 1 1 100.00
lc_ctrl_csr_rw 0.840s 15.456us 1 1 100.00
lc_ctrl_csr_aliasing 1.700s 407.568us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 121.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.600s 48.312us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1154.190us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.600s 48.312us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.930s 300.022us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1154.190us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1154.190us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1154.190us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1154.190us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1154.190us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1154.190us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1154.190us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.090s 305.051us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1154.190us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.760s 292.396us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.450s 595.259us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.280s 1367.237us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.800s 326.840us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.800s 326.840us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.070s 1162.520us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.520s 976.008us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.520s 976.008us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 65.340s 2994.515us 1 1 100.00