Simulation Results: lc_ctrl/volatile_unlock_enabled

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.62 %
  • code
  • 84.21 %
  • assert
  • 93.72 %
  • func
  • 90.93 %
  • line
  • 97.06 %
  • branch
  • 93.92 %
  • cond
  • 79.14 %
  • toggle
  • 88.32 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.770s 518.480us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.920s 52.217us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.060s 28.152us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.130s 40.064us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 24.524us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.290s 39.162us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.060s 28.152us 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 24.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.980s 76.807us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.490s 825.775us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.120s 21.083us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.320s 184.540us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.310s 1587.138us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_ctrl_prog_failure 1.320s 184.540us 1 1 100.00
lc_ctrl_errors 7.310s 1587.138us 1 1 100.00
lc_ctrl_security_escalation 5.650s 333.685us 1 1 100.00
lc_ctrl_jtag_state_failure 42.170s 1772.707us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.610s 867.907us 1 1 100.00
lc_ctrl_jtag_errors 35.620s 3080.518us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.140s 195.692us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.970s 1764.033us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.610s 867.907us 1 1 100.00
lc_ctrl_jtag_errors 35.620s 3080.518us 1 1 100.00
lc_ctrl_jtag_access 1.670s 199.130us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.640s 3745.470us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.800s 77.922us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.120s 248.850us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.030s 467.780us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.940s 1352.125us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.300s 42.545us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.680s 320.738us 1 1 100.00
lc_ctrl_jtag_alert_test 1.160s 120.300us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.880s 374.955us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.770s 45.418us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 71.060s 13467.148us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.950s 49.143us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.980s 45.637us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.980s 45.637us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 52.217us 1 1 100.00
lc_ctrl_csr_rw 1.060s 28.152us 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 24.524us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 44.433us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 52.217us 1 1 100.00
lc_ctrl_csr_rw 1.060s 28.152us 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 24.524us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 44.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.510s 1086.053us 1 1 100.00
lc_ctrl_tl_intg_err 1.800s 82.726us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.800s 82.726us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.490s 825.775us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1086.053us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1086.053us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1086.053us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1086.053us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1086.053us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1086.053us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1086.053us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.580s 580.394us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1086.053us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.650s 333.685us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.980s 76.807us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.970s 1764.033us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.910s 214.365us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.910s 214.365us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.520s 363.457us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.380s 1492.722us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.380s 1492.722us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 26.330s 5160.296us 1 1 100.00