Simulation Results: otbn

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.54 %
  • code
  • 95.26 %
  • assert
  • 89.60 %
  • func
  • 95.76 %
  • block
  • 99.38 %
  • line
  • 99.57 %
  • branch
  • 92.30 %
  • toggle
  • 91.74 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 72.362us 1 1 100.00
single_binary 1 1 100.00
otbn_single 16.000s 60.612us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 21.790us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 28.883us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 471.365us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 17.084us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 34.775us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 28.883us 1 1 100.00
otbn_csr_aliasing 4.000s 17.084us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 35.000s 2295.470us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 42.000s 2380.608us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 16.000s 208.777us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 45.000s 320.957us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 32.000s 170.725us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 10.000s 45.886us 1 1 100.00
lc_escalation 0 1 0.00
otbn_escalate 3.000s 1.647us 0 1 0.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 36.180us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 35.851us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 3.000s 17.323us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 36.973us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 1211.245us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 1211.245us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 21.790us 1 1 100.00
otbn_csr_rw 3.000s 28.883us 1 1 100.00
otbn_csr_aliasing 4.000s 17.084us 1 1 100.00
otbn_same_csr_outstanding 4.000s 78.651us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 21.790us 1 1 100.00
otbn_csr_rw 3.000s 28.883us 1 1 100.00
otbn_csr_aliasing 4.000s 17.084us 1 1 100.00
otbn_same_csr_outstanding 4.000s 78.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 6.000s 12.527us 1 1 100.00
otbn_dmem_err 7.000s 16.919us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 6.000s 19.643us 1 1 100.00
otbn_controller_ispr_rdata_err 21.000s 159.627us 1 1 100.00
otbn_mac_bignum_acc_err 6.000s 195.982us 1 1 100.00
otbn_urnd_err 4.000s 10.420us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.688us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 34.393us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 135.342us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_tl_intg_err 8.000s 235.147us 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 36.000s 781.296us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 72.362us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 16.919us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 6.000s 12.527us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 8.000s 235.147us 1 1 100.00
sec_cm_controller_fsm_global_esc 0 1 0.00
otbn_escalate 3.000s 1.647us 0 1 0.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 6.000s 12.527us 1 1 100.00
otbn_dmem_err 7.000s 16.919us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 36.180us 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.688us 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 16.000s 60.612us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 6.000s 12.527us 1 1 100.00
otbn_dmem_err 7.000s 16.919us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 36.180us 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.688us 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 0 1 0.00
otbn_escalate 3.000s 1.647us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 6.000s 12.527us 1 1 100.00
otbn_dmem_err 7.000s 16.919us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 36.180us 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.688us 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 16.000s 60.612us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 55.391us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 12.000s 51.070us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 42.000s 132.460us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 42.000s 132.460us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 6.000s 27.954us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 6.000s 250.728us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 10.057us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 10.057us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 16.000s 89.822us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 60.612us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 60.612us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 16.000s 60.612us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 32.000s 170.725us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 16.000s 60.612us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 16.000s 60.612us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 21.922us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 16.000s 60.612us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 101.000s 1135.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 126.000s 3148.824us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 20.853us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_escalate 96901340091065430750644641763654864313450213543900986680506731668907382642488 109
UVM_ERROR @ 1647092 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 1647092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 34434568867389754108302100068558886404912541225335949665796197456342411253825 384
UVM_ERROR @ 3148824152 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3148824152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_stack_addr_integ_chk 107196695438879489933321476302510176327236793824865739515574300340939031100343 119
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 10057393 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 10057393 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 10057393 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 10057393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---