Simulation Results: otp_ctrl

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.11 %
  • code
  • 77.82 %
  • assert
  • 93.99 %
  • func
  • 71.53 %
  • line
  • 88.65 %
  • branch
  • 83.22 %
  • cond
  • 90.27 %
  • toggle
  • 83.54 %
  • FSM
  • 43.40 %
Validation stages
V1
100.00%
V2
90.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.440s 131.265us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.710s 192.567us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.410s 347.710us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.360s 516.740us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 2.790s 166.347us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.620s 104.020us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.170s 121.271us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.360s 516.740us 1 1 100.00
otp_ctrl_csr_aliasing 2.620s 104.020us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.470s 60.561us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.750s 473.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 18.260s 323.115us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.730s 466.258us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 13.300s 1240.288us 1 1 100.00
otp_ctrl_check_fail 2.120s 135.547us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.200s 617.817us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 19.030s 3181.372us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 4.970s 405.265us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 13.140s 2219.248us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 15.670s 1244.074us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.950s 116.042us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 13.690s 4323.322us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 30.750s 11944.840us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.400s 149.798us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.750s 134.696us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.710s 436.370us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.710s 436.370us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.410s 347.710us 1 1 100.00
otp_ctrl_csr_rw 2.360s 516.740us 1 1 100.00
otp_ctrl_csr_aliasing 2.620s 104.020us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.070s 291.035us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.410s 347.710us 1 1 100.00
otp_ctrl_csr_rw 2.360s 516.740us 1 1 100.00
otp_ctrl_csr_aliasing 2.620s 104.020us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.070s 291.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 12.450s 2909.518us 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.450s 2909.518us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.710s 192.567us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.710s 192.567us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
otp_ctrl_macro_errs 1.950s 116.042us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
otp_ctrl_macro_errs 1.950s 116.042us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.180s 123.942us 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.730s 466.258us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.120s 135.547us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 19.030s 3181.372us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 19.030s 3181.372us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 19.030s 3181.372us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 19.030s 3181.372us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 19.030s 3181.372us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.710s 192.567us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 19.030s 3181.372us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.710s 192.567us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 157.460s 166819.915us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.200s 617.817us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.710s 192.567us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.710s 192.567us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.950s 116.042us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.470s 5954.418us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.140s 53.051us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 29064823737637392552302717704775303486571338995809617032979362468551264911844 535
UVM_ERROR @ 135546750 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 135546750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:*
otp_ctrl_macro_errs 85157257926521767869750959517108719983130321976570115314586861046530653207765 644
UVM_ERROR @ 116041547 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 116041547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 70418417022784709312534820040361018819980847195773392796544960683695340195841 93
UVM_ERROR @ 53050567 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53050567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---