Simulation Results: pattgen

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 6.000s 45.611us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 11.192us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 56.553us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 129.243us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 101.552us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 26.906us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 56.553us 1 1 100.00
pattgen_csr_aliasing 1.000s 101.552us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 479.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 8.000s 1097.776us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 13.362us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 2.000s 1470.905us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 13.291us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 52.219us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 73.064us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 73.064us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 11.192us 1 1 100.00
pattgen_csr_rw 1.000s 56.553us 1 1 100.00
pattgen_csr_aliasing 1.000s 101.552us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 18.520us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 11.192us 1 1 100.00
pattgen_csr_rw 1.000s 56.553us 1 1 100.00
pattgen_csr_aliasing 1.000s 101.552us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 18.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 157.000us 1 1 100.00
pattgen_tl_intg_err 1.000s 143.182us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 143.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
pattgen_stress_all_with_rand_reset 14.000s 8848.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 1.000s 40.686us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pattgen_perf 75774525632613406999874850627990805456937291037067972243949652208648703800062 99
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 32704583457584594994545222607764500079729557878093670926054880150327558243746 142
UVM_ERROR @ 1470904968 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10277