Simulation Results: pwm

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.50 %
  • code
  • 96.14 %
  • assert
  • 98.00 %
  • func
  • 98.35 %
  • block
  • 99.02 %
  • line
  • 99.28 %
  • branch
  • 98.27 %
  • toggle
  • 90.87 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwm_smoke 3.000s 536.700us 1 1 100.00
csr_hw_reset 1 1 100.00
pwm_csr_hw_reset 1.000s 114.911us 1 1 100.00
csr_rw 1 1 100.00
pwm_csr_rw 1.000s 17.910us 1 1 100.00
csr_bit_bash 1 1 100.00
pwm_csr_bit_bash 3.000s 507.968us 1 1 100.00
csr_aliasing 1 1 100.00
pwm_csr_aliasing 2.000s 81.809us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwm_csr_mem_rw_with_rand_reset 2.000s 85.135us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwm_csr_rw 1.000s 17.910us 1 1 100.00
pwm_csr_aliasing 2.000s 81.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 1 1 100.00
pwm_rand_output 33.000s 43761.260us 1 1 100.00
pulse 1 1 100.00
pwm_rand_output 33.000s 43761.260us 1 1 100.00
blink 1 1 100.00
pwm_rand_output 33.000s 43761.260us 1 1 100.00
heartbeat 1 1 100.00
pwm_rand_output 33.000s 43761.260us 1 1 100.00
resolution 1 1 100.00
pwm_rand_output 33.000s 43761.260us 1 1 100.00
multi_channel 1 1 100.00
pwm_rand_output 33.000s 43761.260us 1 1 100.00
polarity 1 1 100.00
pwm_rand_output 33.000s 43761.260us 1 1 100.00
phase 2 2 100.00
pwm_rand_output 33.000s 43761.260us 1 1 100.00
pwm_phase 25.000s 10720.014us 1 1 100.00
lowpower 1 1 100.00
pwm_rand_output 33.000s 43761.260us 1 1 100.00
perf 1 1 100.00
pwm_perf 26.000s 41991.970us 1 1 100.00
regwen 0 1 0.00
pwm_regwen 51.000s 12712.223us 0 1 0.00
stress_all 1 1 100.00
pwm_stress_all 91.000s 34452.043us 1 1 100.00
alert_test 1 1 100.00
pwm_alert_test 1.000s 12.998us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwm_tl_errors 1.000s 167.728us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwm_tl_errors 1.000s 167.728us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwm_csr_hw_reset 1.000s 114.911us 1 1 100.00
pwm_csr_rw 1.000s 17.910us 1 1 100.00
pwm_csr_aliasing 2.000s 81.809us 1 1 100.00
pwm_same_csr_outstanding 2.000s 504.120us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwm_csr_hw_reset 1.000s 114.911us 1 1 100.00
pwm_csr_rw 1.000s 17.910us 1 1 100.00
pwm_csr_aliasing 2.000s 81.809us 1 1 100.00
pwm_same_csr_outstanding 2.000s 504.120us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwm_sec_cm 1.000s 291.270us 1 1 100.00
pwm_tl_intg_err 2.000s 147.437us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwm_tl_intg_err 2.000s 147.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 1 1 100.00
pwm_heartbeat_wrap 36.000s 21002.085us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.pwm_param_* (addr=*)
pwm_regwen 44758587405528439299659216771272260220598786586350135892738424488847074630853 107
UVM_FATAL @ 12712223441 ps: (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.pwm_param_2 (addr=0xb3b2b91c)
UVM_INFO @ 12712223441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---