Simulation Results

Simulation Results: pwrmgr

07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.52 %

code
94.66 %

assert
95.04 %

func
96.87 %

line
98.92 %

branch
95.61 %

cond
94.77 %

toggle
90.02 %

FSM
94.00 %

Validation stages

V1		100.00%
V2		93.33%
V2S		80.00%
V3		50.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	pwrmgr_smoke	0.860s	29.843us	1	1	100.00
csr_hw_reset				1	1	100.00
	pwrmgr_csr_hw_reset	0.750s	92.355us	1	1	100.00
csr_rw				1	1	100.00
	pwrmgr_csr_rw	0.690s	20.199us	1	1	100.00
csr_bit_bash				1	1	100.00
	pwrmgr_csr_bit_bash	2.080s	221.747us	1	1	100.00
csr_aliasing				1	1	100.00
	pwrmgr_csr_aliasing	1.000s	27.344us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	pwrmgr_csr_mem_rw_with_rand_reset	1.130s	48.783us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	pwrmgr_csr_rw	0.690s	20.199us	1	1	100.00
	pwrmgr_csr_aliasing	1.000s	27.344us	1	1	100.00

14/15 passed

93.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wakeup				1	1	100.00
	pwrmgr_wakeup	0.690s	65.611us	1	1	100.00
control_clks				1	1	100.00
	pwrmgr_wakeup	0.690s	65.611us	1	1	100.00
aborted_low_power				2	2	100.00
	pwrmgr_aborted_low_power	0.760s	45.717us	1	1	100.00
	pwrmgr_lowpower_invalid	0.680s	51.545us	1	1	100.00
reset				1	2	50.00
	pwrmgr_reset	1.280s	1000.000us	0	1	0.00
	pwrmgr_reset_invalid	0.750s	125.573us	1	1	100.00
main_power_glitch_reset				0	1	0.00
	pwrmgr_reset	1.280s	1000.000us	0	1	0.00
reset_wakeup_race				1	1	100.00
	pwrmgr_wakeup_reset	1.020s	199.563us	1	1	100.00
lowpower_wakeup_race				1	1	100.00
	pwrmgr_lowpower_wakeup_race	0.630s	76.849us	1	1	100.00
disable_rom_integrity_check				1	1	100.00
	pwrmgr_disable_rom_integrity_check	0.920s	153.813us	1	1	100.00
stress_all				1	1	100.00
	pwrmgr_stress_all	1.920s	1241.410us	1	1	100.00
intr_test				1	1	100.00
	pwrmgr_intr_test	0.690s	22.496us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	pwrmgr_tl_errors	1.430s	106.339us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	pwrmgr_tl_errors	1.430s	106.339us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.750s	92.355us	1	1	100.00
	pwrmgr_csr_rw	0.690s	20.199us	1	1	100.00
	pwrmgr_csr_aliasing	1.000s	27.344us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.660s	21.932us	1	1	100.00
tl_d_partial_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.750s	92.355us	1	1	100.00
	pwrmgr_csr_rw	0.690s	20.199us	1	1	100.00
	pwrmgr_csr_aliasing	1.000s	27.344us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.660s	21.932us	1	1	100.00

V2S

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	2	0.00
	pwrmgr_sec_cm	0.680s	21.744us	0	1	0.00
	pwrmgr_tl_intg_err	0.630s	10.725us	0	1	0.00
prim_count_check				0	1	0.00
	pwrmgr_sec_cm	0.680s	21.744us	0	1	0.00
prim_fsm_check				0	1	0.00
	pwrmgr_sec_cm	0.680s	21.744us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	pwrmgr_tl_intg_err	0.630s	10.725us	0	1	0.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.990s	747.924us	1	1	100.00
sec_cm_rom_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_wakeup_reset	1.020s	199.563us	1	1	100.00
sec_cm_rstmgr_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.010s	71.371us	1	1	100.00
sec_cm_esc_rx_clk_bkgn_chk				1	1	100.00
	pwrmgr_esc_clk_rst_malfunc	0.620s	31.448us	1	1	100.00
sec_cm_esc_rx_clk_local_esc				0	1	0.00
	pwrmgr_sec_cm	0.680s	21.744us	0	1	0.00
sec_cm_fsm_sparse				0	1	0.00
	pwrmgr_sec_cm	0.680s	21.744us	0	1	0.00
sec_cm_fsm_terminal				0	1	0.00
	pwrmgr_sec_cm	0.680s	21.744us	0	1	0.00
sec_cm_ctrl_flow_global_esc				1	1	100.00
	pwrmgr_global_esc	0.730s	29.901us	1	1	100.00
sec_cm_main_pd_rst_local_esc				1	1	100.00
	pwrmgr_glitch	0.710s	72.698us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	pwrmgr_sec_cm_ctrl_config_regwen	0.730s	137.335us	1	1	100.00
sec_cm_wakeup_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.690s	20.199us	1	1	100.00
sec_cm_reset_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.690s	20.199us	1	1	100.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
escalation_timeout				0	1	0.00
	pwrmgr_escalation_timeout	0.870s	184.092us	0	1	0.00
stress_all_with_rand_reset				1	1	100.00
	pwrmgr_stress_all_with_rand_reset	2.640s	822.047us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	pwrmgr_reset	19932255086095550779223080782956600151357400419380753995654242412402618517944	139	UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((!clk_en) \|\| status)'
	pwrmgr_escalation_timeout	94792083711094963655925433151885598180459526563710876678006189768022613981547	79	Offending '((!clk_en) \|\| status)' UVM_ERROR @ 184092463 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A UVM_INFO @ 184092463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
	pwrmgr_sec_cm	112233832007971388047103181831856546279473058140478121289250642091035665484724	82	UVM_ERROR @ 21744400 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 21744400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_tl_intg_err	98461065819612929403892528602869126809438683318126879685954585397073596317444	82	UVM_ERROR @ 10725420 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 10725420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---