Simulation Results: rom_ctrl/32kb

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.26 %
  • code
  • 98.22 %
  • assert
  • 96.65 %
  • func
  • 96.90 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.22 %
  • toggle
  • 99.97 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.890s 180.864us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.480s 548.426us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.510s 125.028us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.650s 307.873us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.630s 552.944us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.400s 211.372us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.510s 125.028us 1 1 100.00
rom_ctrl_csr_aliasing 3.630s 552.944us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.010s 963.378us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.300s 197.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.170s 1070.980us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.900s 608.451us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.320s 222.681us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.770s 536.478us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.360s 172.552us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.360s 172.552us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.480s 548.426us 1 1 100.00
rom_ctrl_csr_rw 3.510s 125.028us 1 1 100.00
rom_ctrl_csr_aliasing 3.630s 552.944us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.450s 540.698us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.480s 548.426us 1 1 100.00
rom_ctrl_csr_rw 3.510s 125.028us 1 1 100.00
rom_ctrl_csr_aliasing 3.630s 552.944us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.450s 540.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.460s 409.829us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 103.310s 810.943us 1 1 100.00
rom_ctrl_tl_intg_err 24.580s 337.746us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 103.310s 810.943us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 103.310s 810.943us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.310s 810.943us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 103.310s 810.943us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.890s 180.864us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.890s 180.864us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.890s 180.864us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.580s 337.746us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
rom_ctrl_kmac_err_chk 6.320s 222.681us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.060s 13627.650us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.460s 409.829us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.310s 810.943us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 169.400s 2736.422us 1 1 100.00