Simulation Results: rom_ctrl/64kb

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.28 %
  • code
  • 97.90 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.22 %
  • toggle
  • 99.24 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.520s 300.177us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.670s 1078.977us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.840s 327.303us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.240s 3334.408us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.350s 1030.327us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.380s 237.701us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.840s 327.303us 1 1 100.00
rom_ctrl_csr_aliasing 7.350s 1030.327us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 9.220s 3976.623us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.080s 1118.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.450s 313.139us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 22.310s 1574.678us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 15.050s 544.799us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.490s 1068.209us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.280s 220.180us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.280s 220.180us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.670s 1078.977us 1 1 100.00
rom_ctrl_csr_rw 6.840s 327.303us 1 1 100.00
rom_ctrl_csr_aliasing 7.350s 1030.327us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.020s 1113.174us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.670s 1078.977us 1 1 100.00
rom_ctrl_csr_rw 6.840s 327.303us 1 1 100.00
rom_ctrl_csr_aliasing 7.350s 1030.327us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.020s 1113.174us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.270s 2161.222us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 223.630s 915.991us 1 1 100.00
rom_ctrl_tl_intg_err 52.660s 473.404us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 223.630s 915.991us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 223.630s 915.991us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 223.630s 915.991us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 223.630s 915.991us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.520s 300.177us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.520s 300.177us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.520s 300.177us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 52.660s 473.404us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
rom_ctrl_kmac_err_chk 15.050s 544.799us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.240s 3952.277us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.270s 2161.222us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 223.630s 915.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 239.400s 4707.742us 1 1 100.00