Simulation Results: rstmgr

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.94 %
  • code
  • 99.31 %
  • assert
  • 97.99 %
  • func
  • 96.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.080s 124.446us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.930s 81.499us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.860s 86.453us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.980s 1027.408us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.350s 107.945us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.470s 189.749us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.860s 86.453us 1 1 100.00
rstmgr_csr_aliasing 1.350s 107.945us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.840s 188.200us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.290s 130.575us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.400s 189.608us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.330s 1612.372us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.330s 1612.372us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.330s 1612.372us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.330s 1612.372us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 6.060s 1828.539us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.800s 93.939us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.850s 285.746us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.850s 285.746us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.930s 81.499us 1 1 100.00
rstmgr_csr_rw 0.860s 86.453us 1 1 100.00
rstmgr_csr_aliasing 1.350s 107.945us 1 1 100.00
rstmgr_same_csr_outstanding 1.190s 104.285us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.930s 81.499us 1 1 100.00
rstmgr_csr_rw 0.860s 86.453us 1 1 100.00
rstmgr_csr_aliasing 1.350s 107.945us 1 1 100.00
rstmgr_same_csr_outstanding 1.190s 104.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 1.880s 516.211us 1 1 100.00
rstmgr_sec_cm 19.980s 16923.883us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.980s 16923.883us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.980s 16923.883us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.880s 516.211us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.890s 104.070us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.730s 2477.964us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.030s 301.293us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.980s 16923.883us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.860s 86.453us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.860s 86.453us 1 1 100.00