Simulation Results: rv_timer

 
07/04/2026 19:25:09 DVSim: v1.17.3 sha: f66d746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.18 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 94.71 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.420s 919.464us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.550s 58.516us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 43.192us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.640s 237.557us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.690s 31.480us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.070s 104.944us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 43.192us 1 1 100.00
rv_timer_csr_aliasing 0.690s 31.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.030s 452.030us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.390s 2945.211us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 9.670s 24758.563us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 9.670s 24758.563us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.690s 6671.821us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.720s 14.655us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.720s 45.864us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.580s 78.957us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.580s 78.957us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 58.516us 1 1 100.00
rv_timer_csr_rw 0.560s 43.192us 1 1 100.00
rv_timer_csr_aliasing 0.690s 31.480us 1 1 100.00
rv_timer_same_csr_outstanding 0.660s 275.080us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 58.516us 1 1 100.00
rv_timer_csr_rw 0.560s 43.192us 1 1 100.00
rv_timer_csr_aliasing 0.690s 31.480us 1 1 100.00
rv_timer_same_csr_outstanding 0.660s 275.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.960s 468.567us 1 1 100.00
rv_timer_tl_intg_err 1.190s 198.871us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.190s 198.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.790s 847.431us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.060s 41.929us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 13.330s 19113.455us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 70480184953527264393337233360368044151433288671184292656920096399393524071402 75
UVM_FATAL @ 847431183 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x745b704) == 0x1
UVM_INFO @ 847431183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 35839487897776541565542061828668374684985100411012067916679231886651427979194 75
UVM_FATAL @ 452029857 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc4c6cb04) == 0x1
UVM_INFO @ 452029857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 1112738236771707008710307101071052474970373566364942689714933754093325608636 75
UVM_ERROR @ 41928960 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 41928960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---